JPS6095666A - インタフエ−ス制御方法 - Google Patents

インタフエ−ス制御方法

Info

Publication number
JPS6095666A
JPS6095666A JP20229983A JP20229983A JPS6095666A JP S6095666 A JPS6095666 A JP S6095666A JP 20229983 A JP20229983 A JP 20229983A JP 20229983 A JP20229983 A JP 20229983A JP S6095666 A JPS6095666 A JP S6095666A
Authority
JP
Japan
Prior art keywords
message
interface
input
output control
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20229983A
Other languages
English (en)
Japanese (ja)
Other versions
JPS64737B2 (cs
Inventor
Seiichi Sugaya
菅谷　誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20229983A priority Critical patent/JPS6095666A/ja
Publication of JPS6095666A publication Critical patent/JPS6095666A/ja
Publication of JPS64737B2 publication Critical patent/JPS64737B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
JP20229983A 1983-10-28 1983-10-28 インタフエ−ス制御方法 Granted JPS6095666A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20229983A JPS6095666A (ja) 1983-10-28 1983-10-28 インタフエ−ス制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20229983A JPS6095666A (ja) 1983-10-28 1983-10-28 インタフエ−ス制御方法

Publications (2)

Publication Number Publication Date
JPS6095666A true JPS6095666A (ja) 1985-05-29
JPS64737B2 JPS64737B2 (cs) 1989-01-09

Family

ID=16455241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20229983A Granted JPS6095666A (ja) 1983-10-28 1983-10-28 インタフエ−ス制御方法

Country Status (1)

Country Link
JP (1) JPS6095666A (cs)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5258432A (en) * 1975-11-10 1977-05-13 Nec Corp Common bus control circuit
JPS56159750A (en) * 1980-05-14 1981-12-09 Toshiba Corp Bus control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5258432A (en) * 1975-11-10 1977-05-13 Nec Corp Common bus control circuit
JPS56159750A (en) * 1980-05-14 1981-12-09 Toshiba Corp Bus control system

Also Published As

Publication number Publication date
JPS64737B2 (cs) 1989-01-09

Similar Documents

Publication Publication Date Title
US4275440A (en) I/O Interrupt sequencing for real time and burst mode devices
EP1386219B1 (en) Entering and exiting power managed states without disrupting accelerated graphics port transactions
US5812875A (en) Apparatus using a state device and a latching circuit to generate an acknowledgement signal in close proximity to the request signal for enhancing input/output controller operations
JPH0690699B2 (ja) 割込インタフェース回路
JPH05282241A (ja) バーストデータ転送装置および方法
JP2001524707A (ja) コントローラの機能性を高めるためのファームウェアの使用
US5572684A (en) IEEE 488 interface and message handling method
US20070240011A1 (en) FIFO memory data pipelining system and method for increasing I²C bus speed
JPS6339072A (ja) デ−タ処理システム
US7366809B2 (en) Pipelined stop, start, address byte, and data byte technique and circuit for I2C logic system
JPS6095666A (ja) インタフエ−ス制御方法
US7577877B2 (en) Mechanisms to prevent undesirable bus behavior
JP2004334840A (ja) システムバスの制御方法及び関連装置
JP3261665B2 (ja) データ転送方法及びデータ処理システム
RU2018944C1 (ru) Устройство для сопряжения эвм с внешними объектами
JP2638505B2 (ja) バスインタフェース装置
JPS5810226A (ja) デ−タ処理装置
JPH076133A (ja) データ転送方法及びデータ処理システム
CN118689815A (zh) 用于串行外设接口spi通信的方法及装置、spi通信设备
US7085864B1 (en) Method and structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter
JPS63192152A (ja) デ−タ伝送方式
JPH103463A (ja) プロセッサ間通信方法
JPS5922462A (ja) 通信制御方式
KR20010054137A (ko) 시스템 효율을 향상시키는 버스 제어방법
JPS6359181B2 (cs)