JPS6095653A - Zone generating circuit - Google Patents

Abstract

PURPOSE:To increase easily a bit pattern to be generated, by dividing an area of the pattern into divided areas of prescribed size,and selecting and outputting one from the bit patterns of five kinds at every divided area. CONSTITUTION:Numbers 1A, 2A of divided areas to which the start point and the end point belong, and bit numbers 1B, 2B for showing an address of its bit unit are stored in a start point information register 1 and an end point information register 2, respectively. These data are sent to bit pattern generating means 3-6, and the bit pattern generating means 3 sends a bit pattern of a devided area unit to a judging means 9. The bit patern generating means 4-8 generate bit patterns of five kinds, and output them to a selecting means 10. The judging means 9 sends a selecting signal to the selecting means 10, and a bit pattern for showing a closed section indicated by the start point and the end point in the area is outputted from the selecting means 10.

Description

TECHNICAL FIELD The present invention relates to a zone generation circuit for generating a bit pattern representing a closed section within an area in an information processing apparatus.

A prior art zone generation circuit is used in a circuit for a data write function to a memory of an information processing device, especially a partial write function.

This zone generation circuit generates a bit pattern indicating the portion of data to be written to the memory. Generally, partial writing to memory is performed in byte units, and the number of bits of the generated bit pattern is not so large. For this reason, the conventional zone generation circuit has a means for generating consecutive bits of t1m by the same number of bits as the number of bytes of data to be partially written, and a means for generating consecutive bits of 9'''1''.
It has a simple structure consisting of means for moving the data to the same position as the partial write data in the data using the start point information, and setting the other bits to '0''.

This conventional zone generation circuit has the disadvantage that when the number of bits of the generated bit pattern is increased, the hardware of the two means described above increases in proportion to the increased number of bits.

OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide a zone generation circuit in which increasing the number of bits of a bit pattern to be generated does not require a proportional increase in hardware.

Structure of the Invention For this reason (2), instead of directly generating all bits of a bit pattern, the zone generation circuit of the present invention divides the area into divided areas of a predetermined size, and generates the divided area to which the starting point belongs and the divided area. means for storing starting point information indicating the address of the starting point within, and end point information indicating the divided area to which the ending point belongs and the address of the ending point within the divided area;
Means for generating a bit pattern indicating a closed interval for each divided area from start point information and end point information, 5 types of bit pattern generation means for generating 5 types of bit patterns that the divided area can handle, and 5 types of bit pattern generation means for each divided area. Among the 5 types of bit patterns from the bit patterns indicating the closed interval of
A determining means for determining which one corresponds to the divided area; and a selecting means for selecting one of the five types of bit patterns for each divided area according to this determination, and outputting the selected one from all the bits of the bit pattern. It is something that generates.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a zone generation circuit according to an embodiment of the present invention. The starting point information register 1 stores the number IA of the divided area to which the starting point S belongs and the bit number IB indicating the bit-by-bit address of the starting point S within the divided area. Similarly, the end point information register 2 stores two numbers of the divided area to which the end point E belongs and a bit number 2B indicating the address of the end point E in pit units within the divided area. The starting point information register 1 and the ending point information register 2 have the number of bits necessary to indicate the area from end to end.

The data of divided area numbers IA and 2A are sent to the bit pattern generating means 3 which generates a bit pattern indicating a closed interval in each divided area, and the data of bit numbers IB and 2B generate a bit pattern within the divided area. It is sent to bit pattern generating means 4-6. The bit pattern generating means 3 sends the bit pattern for each divided area to the determining means 9. The bit pattern generation means 4 to 8 generate five types of bit patterns and output them to the selection means 10. .

In other words, the bit pattern generating means 4 generates the bit pattern within the divided area (
The bit pattern generating means 5 generates a bit pattern when there are two starting points S, the bit pattern generating means 6 generates a bit pattern when there is an ending point E in the divided area, and the bit pattern generating means 6 generates a bit pattern when there is a starting point S and an ending point E in the divided area. The bit pattern generating means 7 generates a bit pattern when there is neither a start point S nor an end point E in the divided area, and the divided area is located between the start point S and the end point E, that is, within a closed interval. The means 8 generates bit patterns when there is neither a starting point S nor an ending point E within the divided area, and the divided area is located outside between the starting point S and the ending point E, that is, outside the closed interval. The determining means 9 generates a selection signal for the bit pattern within the divided area for each divided area from the bit pattern for each divided area sent from the bit pattern generating means 3, and sends it to the selecting means 10. The selection means 10 selects and outputs one of the five types of bit patterns described above based on the selection signal from the determination means 9 for each divided area. Therefore, the output of the selection means 10 becomes a bit pattern representing a closed section indicated by the starting point S and the ending point E within the area.

Next, the operation of the zone generating circuit shown in FIG. 1 having the above configuration will be explained based on specific data.

It is assumed that the number of divided areas is 8, the size of the divided area is 8 bits, and the data shown in Figure 2 (1) and (2) are stored in starting point information register 1 and ending point information register 2, respectively. . In other words, the number of the divided area to which the starting point S belongs is l, and the number indicating the position within the divided area is -77.
The number is 2, and the bit pattern that should be generated in the divided circuit to which the end point E belongs is shown in Figure 2 (3), that is, 10 consecutive bits starting from the beginning.
The bit pattern is a pit "0", followed by a series of 36 pits of 1", and then a series of 18 bits of 0".

The numbers at the top of FIG. 2 (3) are the numbers of the divided areas. Note that the starting point S and ending point E are outside the area (if there are two,
Starting point information register 1 contains ooooo indicating the left end of the area.
"o" indicates the right end of the area in the end point information register 2.
Data 111111' is stored. When both the starting point S and the ending point E are outside the area (2), the bit pattern that should be generated is a bit pattern in which all 1'' are shown. (4), (51, (61, (7), +81) respectively indicate the bit patterns generated by the bit pattern generating means 4.5.6.7.8.The bit pattern generating means 4 generates the data of bit number IB of the starting point information register 1.
010", the bit pattern "'0011111" in which all the right side from the starting point S (second bit) is @1"
The bit pattern generating means 5 receives the data "101" of bit number 2B of the end point information register 2 and generates a bit pattern "11111100" in which all the left side of the end point E (fifth bit) is 1M. ” occurs.

The bit pattern generating means 6 generates the data "'010" of bit number IB of the starting point information register 1 and the ending point information register 2.
After receiving the data "101" of bit number 2B, start point S
A bit pattern 00111100# with "1#" between (second pit) and end point E (fifth bit) is generated.

The bit pattern generating means 7 generates a pattern "'l#α" when there is neither a starting point S nor an ending point E in the divided area and the divided area is located between the starting point S and the ending point E.The bit pattern generating means 8 generates a bit pattern where all bits are '0#' when there is neither a start point S nor an end point E within the divided area, and the divided area is located outside between the start point S and the end point E.

The bit pattern of the bit pattern generating means 7.8 is a fixed output unrelated to the data of the start point information register 1 and the end point information register 2. The bit pattern generating means 3 generates data @001 of number IA of the divided area of the starting point information register 1.
' and the divided area number 2 data "101" of the end point information register 2 are received, and the bit pattern "01111100" with the divided area as a unit as shown in FIG. 2 (9) (2) is received.
” is generated. The determining means 9 is the bit pattern generating means 3.
Based on the bit pattern generated from the bit pattern generating means 4 to 9, a bit pattern (selection signal) is generated for determining which bit pattern corresponds to the divided area among the bit patterns generated from the bit pattern generating means 4 to 9. The selection signal is generated by checking, for each divided area, the states of the bits in the bit pattern generated by the bit pattern generating means 3 in the divided area and the divided areas before and after it.

In other words, the bit to the left of divided area number 0 is set to 0'', and this 1110# and bit ``'0'' of divided area number 0 are
, bit ``'1'' of divided area number 1 to 'OO1''
Then, a selection signal of "011" is generated from the bit value of the divided area number O11,2.

In this way, the bit pattern output from the bit pattern generating means 3 is shifted one pit at a time to the right from the left side, and three bits are taken at a time to generate a selection signal. Note that the bit to the right of divided area number 7 is set to 0#. Therefore, the selection signal output from the determining means 9 is as shown in FIG.
It will be like 101.

When the selection signal is ``001'', ``100'', or ``ooo'', it is determined that the divided area is outside between the start point S and the end point E, and the bit pattern shown in FIG. 2 (8) is output.Selection signal is 111'', it does not include the start point S or the end point E, and the area between the start point S and the end point E (as shown in Fig. 2) is determined to be two divided areas.
7) Output the bit pattern. The selection signal is “011”
'', it is determined that the divided area includes the starting point S, and the area shown in Figure 2 (
4) Output the bit pattern.

When the selection signal is 110'', it is determined that the divided area includes the end point E, and the bit pattern shown in FIG. The bit pattern shown in Figure 2 (6) is output.The number under tlo) in Figure 2 indicates the number of the bit pattern to be output. 10 shows the bit pattern output from the selection means 1O, which matches the bit pattern in FIG. 10 (3).

From the above, when the number of bits in an area is increased, the hardware of each means is the bit pattern generating means 3 and the determining means 9 (both of which have the same number of bits as the divided area, that is, 1 bit for each increase of 8 bits). It can be seen that the output of each of the bit pattern generation means 4 to 8 increases, and the output of the bit pattern generation means 4 to 8 does not increase, and the output of the selection means 10 increases by the same number of bits as the increase in the number of bits of the area.

As described in detail of the invention (2. Even if the number of bits of the bit pattern to be generated is increased, the zone generation circuit of the present invention can improve the performance of all of the bit pattern generation means, determination means, and selection means). The software does not increase proportionally to this increased number of bits (2).

[Brief explanation of drawings]

FIG. 1 is a block diagram of a zone generation circuit according to an embodiment of the present invention, FIG. 2 is a diagram explaining the operation of FIG. 1 based on specific data, and FIG. data, Figure 2 (2) is the data of the end point information register 2, Figure 2 (3) is the bit pattern to be generated by the zone generation circuit, Figure 2 (4), (5), (6), (7). ) and (8) are the bit patterns generated by the bit pattern generating means 4.5.6.7.8, respectively, in FIG. 2 (91 is the bit pattern generated by the bit pattern generating means 3, FIG. 2 uQl
is the bit pattern of the selection signal outputted from the determining means 9, and 211th (11) is the bit pattern outputted from the selection means 1O. 1: Starting point information register 2: Ending point information register 3.4.5.6.7.8: Bit pattern generation means 9
: Judgment means 10: Selection means S: Starting point E: Ending point Patent applicant NEC Corporation

Claims (1)

[Claims] In a zone generation circuit that generates bit pattern information representing a closed interval indicated by a start point and an end point within an area, the area is divided into divided areas of a predetermined size, and the divided area to which the start point belongs and Means for storing starting point information indicating the address of the starting point in the divided area, divided area to which the ending point belongs, and end point information indicating the address of the ending point in the divided area, Bit pattern generating means for generating a bit pattern indicating a section; Bit pattern generating means for generating a bit pattern of a divided area having a starting point from starting point information; Generating a bit pattern of a divided area having an end point from end point information From the bit pattern generation means, starting point information and ending point information,
Judgment means for determining the pit pass indicating a closed section in divided area units, which has a start point and an end point, has a start point and an end point located within the closed section, and is located outside the closed section; . A zone generation circuit comprising: a selection means for selecting one of the bit patterns of the 5s class divided areas for each divided area according to the judgment and outputting the selected bit pattern.