JPS6095636A - Interruption controlling system - Google Patents

Abstract

PURPOSE:To reduce an overhead of a software by constituting so that a gate is interposed in an interruption signal outputted from an interruption controlling LSI, and an interruption signal conforming to the number of interruptions generated simultaneously is generated. CONSTITUTION:A microprocessor 1 sets a flip-flop 11 first basing on a processing program of an interruption controlling LSI3, and an operation of a gate 12 inhibits an interruption signal generated from a controlling LSI3. Therefore, an interruption signal supplied to an SIO2 drops to a ''0'' level. In this case, an interruption signal generated from the interruption controlling LSI3 becomes ''0'', but it becomes ''1'' again when other interruption request arrives, and the interruption request and the SIO2 interruption are reset. By this reset, if an interruption signal exists on a line 103, an outout of the gate 12 becomes a ''1'' level, and the interruption is informed to the microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a relatively small t? The present invention relates to an interrupt control method suitable for use in an information processing system.

[Technical background of the invention and its problems]

With the development of microprocessors and LSIs for controlling their peripherals, it has become possible to construct relatively small information processing systems simply by combining these LSI chips. These L
Data exchange between SIs is realized by software instructions possessed by a microprocessor.

By the way, regarding the combination of these LSI chips, the same 7
No problem will occur if the chips are combined together, but due to the performance of the LSI chip or restrictions on the parts used, LSI chips of some families may be connected and used. FIG. 1 shows an example of the connection configuration of this type of system.

In the figure, 1 is a microprocessor (μCPU), which is the core of this system. 2 is a serial input output (SIO) of the same family as this microprocessor 1, and is a peripheral device that handles serial data.
For example, it is an LSI chip designed as an LSI for interfacing communication lines, floppy disks, etc.

This LSI chip 2 has a built-in interrupt priority logic in addition to its original function (parallel/direct/direct 11 mutual conversion), and can automatically provide an interrupt vector without external logic. In the figure, only the same family 5102 of microprocessor 1 is shown.
Peripheral device control LSIs having interrupt priority logic, such as input data output (PIO), are connected in a daisy chain configuration.

3 is an interrupt control LS I (TNTC).

This interrupt control LSI is the microprocessor 1 mentioned above.
It is a programmable LSI of a different family from the above-mentioned GrosseSafari S, and uses a different method of interrupt fri control from the GrosseSafari S. This interrupt control LSI 3 does not have interrupt priority logic built-in, and this LSI handles interrupt processing.
An LSI unit (not shown) having various interrupt factors (INTREQ), such as a DMA control LSI, is connected. The interrupt control LSI 3 organizes the interrupt requests issued here, and sends the selected interrupt request to its own 5IO2
Tell the interrupt free channel of SIO,? The configuration is such that the notification is sent to the microprocessor 1 via the microprocessor 1.

By the way, suppose that interrupt requests occur simultaneously in the information processing system configured as described above.

In this case, the interrupt signal output from the interrupt control LSI 3 is always held at the 1'' level in the 5IO2. It is well known that this is necessary.

Therefore, the fact that the microprocessor 1 is always held at the "P1" level means that it cannot recognize the occurrence of multiple interrupts.Therefore, conventionally, each interrupt processing program has to check if there are other interrupts. It is often necessary to check whether the program is valid or not, and the programmer has to constantly keep this in mind when programming.As such, in the conventional system configuration described above, the software and programmer overheads were heavy.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and by interposing dirt in the interrupt signal output from the interrupt control LSI and generating 76 interrupt signals corresponding to the number of interrupts that occur simultaneously, The purpose of this invention is to provide an interrupt control method that reduces software overhead.

[Summary of the invention]

→, -input l111 νten L tongue -H6'-+ !
Song Tl hand 7.7 and pay 114 people mu I inserted one fritsuno flop and one anddart between the can control LSI and 810. The flip-flop is set/reset repeatedly every time one interrupt processing is completed based on instructions from the processor unit (this set/reset step is inserted into the interrupt processing program), and is output from the interrupt control LSI. The interrupt signal is supplied to the AND-DART together with this Fritsuno-Frotsuno output, and the result of the AND condition is notified to the SIO here. With the above configuration, the interrupt signal output from the interrupt control LSI is not always held at the "1" level in the SIO, and is changed to 1" and 0 every time one interrupt processing is completed. ”, the interrupt can be reliably notified to the processor unit.

This eliminates the above-mentioned inconvenience even when interrupt requests occur simultaneously, and since each interrupt processing program does not need to be aware of other interrupts, software and programmer overhead can be reduced.

[Embodiments of the invention]

The present invention will be described in detail below using FIG. 2 and subsequent figures. FIG. 2 is a block diagram showing an example of the configuration of an information processing system to which the present invention is applied, and only portions related to the gist of the invention are extracted and shown.

In the figure, blocks with the same numbers as the blocks shown in FIG. 1 have the same names and the same functions as those in FIG. 1, so their descriptions will be omitted here to avoid duplication.

The difference from the conventional example shown in FIG. 1 in terms of hardware is that one flip-flop (F/F 77) and one AND gate (
It is at the point where A12) was inserted.

Fritsuno 70 Tsuno 1no is 91 according to Microno Rocessor 1
It is set/reset every time an interrupt process is completed, and the output from the fritsunofutsuno is supplied to the ANDART 12 together with the output from the interrupt control LSI 3.

The AND gate 12 takes the AND condition of both inputs and then notifies the result to the 5IOJ.

In the figure, 100 is a data transfer path, 101 to 103 are interrupt notification lines through which interrupt signals are propagated, and 104 is a fritz output.

Further, 105 is a control line for status read, which is issued from the microprocessor 1 in order to read the interrupt vector address in the interrupt control LSIJ. Furthermore, 106 is an interrupt request signal line for each Yuzu interrupt factor (input/output crab bit) connected to the interrupt control LSI 3.

FIG. 13 is a timing chart showing the operation of the present invention, and shows signals propagating through each line (101 to 106) shown in FIG. 2, respectively.

Below, while using the timing chart in Figure 3,
The operation of the embodiment shown in the figure will be described in detail.

First, every time each input/output unit such as a DMA control unit (not shown) completes processing, it is necessary to notify the microprocessor 1, so this is notified to the interrupt control LSIJ via the interrupt request signal line 106. do.

The interrupt control LS 1.9 organizes the requests in priority order and outputs an interrupt signal via the signal line 103. By the way, since the Fritsuno 70 and Tsuno1no have been initialized (reset state), the interrupt signal is outputted on the line 104 as is. Therefore, and gate 12
The interrupt signal (line 103) supplied to
The next interrupt signal is provided on line 102 to 5IO2.

5IO3 learns of the existence of an interrupt when the interrupt signal propagating through line 102 rises, and in order to entrust the processing to microprocessor 1, it sends a message to microprocessor 1 through line 10. interrupt. According to the above, the interrupt request received by the interrupt control LSI is transmitted to the microprocessor 1, but as mentioned above, the microprocessor family (μCPUJ, 5IO2) and the interrupt control LSI 3 are Since the form of control for the interrupt is different, it is not possible to directly access the address corresponding to the interrupt+request and process it. Therefore, the micro 7'o processor 1 is required to follow the processing procedure shown below.

First, since the interrupt is notified from 5IO2, the microprocessor 1 jumps to the memory address where the program for processing the Sr1 interrupt is stored, and executes the interrupt processing routine.

The processing program for the interrupt control LSI 3 is stored in advance at the address for the 5IO2 interrupt processing.

Based on this processing program, the microprocessor 1
Perform the operations shown below.

First, set the flip frog 11.

When this flip-flop 11 is set, the interrupt signal issued from the interrupt control LSIJ is transmitted to the dart 12.
The prohibition is terminated by activation of SIO, ?
The interrupt signal (line 102) supplied to
fall to the level. Next, interrupt control LS1. Load the vector address (jump address corresponding to the interrupt) in :l to obtain the address for processing the interrupt request. At this time, an interrupt signal (
Line 103) becomes "0#", but when another interrupt request arrives, it becomes "1" again and the next request is made.

Then, the interrupt request is reset and the 5I02 interrupt is reset. SIO,? By resetting the interrupt, 5IO2 will be able to accept the next interrupt.
As mentioned above, a rising nip of the signal propagating through the interrupt No. 46 line 102 is required to generate an interrupt in terms of hardware.

If anddart 12 does not exist and the interrupt control LS
Interrupt signal output by 1.9 (line 103)
is direct SIO,? , the interrupt signal remains in the PIN state, and therefore the SIO 2 does not notify the microprocessor 1 of the interrupt. Therefore,
In order to process the remaining interrupts (which occurred simultaneously), each interrupt processing program reads the contents of the interrupt request register (not shown) built into the interrupt control LSI 3 by reading the READL,
Processing must be performed while checking the presence or absence of other interrupts.

Therefore, in the embodiment of the present invention, flip-flop 1 is reset after processing of one interrupt request is completed. The interrupt control LS1. ? When the inhibition of reception of the interrupt E signal issued from
``level, and a valid interrupt has occurred again. Therefore, this rising signal is sent to 5IO2, and SIO2 notifies the microprocessor 1 as the next interrupt.

〔Effect of the invention〕

As explained above, according to the present invention, even in the 7-stem configuration described above, it is possible to generate interrupt signals that match the number of interrupts that occur simultaneously, so each interrupt processing program can be created without being aware of other interrupts. The possible software and programmer overhead is significantly reduced. Furthermore, once the interrupt processing has started, it is possible to perform an applied operation such as making the next interrupt wait by inhibiting the above-mentioned gate output.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional information processing system, and FIG. 2 is a block diagram showing an example of the configuration of an information processing system to which the present invention is adopted. Both figures show parts related to the gist of the present invention. Only the following are extracted and shown. FIG. 3 is a timing chart showing the operation of the present invention.ノ...Micro processor (μCPU), 2...Serial input meeting output (SIO), 3.
・Interrupt control LSI (INTC), J1・
... Fritsuno 70 Tsuzo (F/F), 12...and dart (A). Fig. 1 Fig. 2 Fig. 3 Separated embryo J

Claims (1)

[Claims] Built-in processor unit and interrupt priority logic,
A peripheral device control LSI of the same Familiar IJ as the processor unit mentioned above is connected to a plurality of input/output crab units that do not have the interrupt priority logic built-in and have interrupt sources, and are used to organize the interrupt requests that will be issued in order of priority and to control the peripheral devices mentioned above. In an information processing system in which interrupt control LSIs that notify interrupts to processor units via LSIs are connected to the same data path, one LSI is installed between the upper interrupt control LSI and the peripheral device control LSI. Each time an interrupt is processed, a flip-flop is set/reset by the processor unit via the data bus, and depending on the flip-flop output, a dart is inserted to inhibit propagation of the interrupt signal issued from the interrupt control LSI. Then, each time one interrupt processing is completed,
An interrupt control method characterized in that, by activating the dart, an interrupt output from the interrupt control LSI is transmitted to the peripheral device control LSI, and a processor unit is notified of the occurrence of the interrupt.