JPS609177A - Thin-film non-linear type resistance element - Google Patents
Thin-film non-linear type resistance elementInfo
- Publication number
- JPS609177A JPS609177A JP11748983A JP11748983A JPS609177A JP S609177 A JPS609177 A JP S609177A JP 11748983 A JP11748983 A JP 11748983A JP 11748983 A JP11748983 A JP 11748983A JP S609177 A JPS609177 A JP S609177A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin film
- resistance element
- film
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims description 38
- 239000012535 impurity Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 99
- 238000000034 method Methods 0.000 abstract description 17
- 239000010408 film Substances 0.000 abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000009719 polyimide resin Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- NZSLSTXKPQAVHL-UHFFFAOYSA-N 2-$l^{1}-oxidanylisoindole-1,3-dione Chemical compound C1=CC=C2C(=O)N([O])C(=O)C2=C1 NZSLSTXKPQAVHL-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QQHSIRTYSFLSRM-UHFFFAOYSA-N alumanylidynechromium Chemical compound [Al].[Cr] QQHSIRTYSFLSRM-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】 効率よく形成するものである。[Detailed description of the invention] It is formed efficiently.
液晶− ＥＬ− Ｅｃ− ＰＤＰ、蛍光表示等の各種表
示装置はいずれも実用化段階に達し一現在の目標は高密
度なマトリクス型表示にあるといえる。Various display devices such as liquid crystal display (EL-Ec-PDP) and fluorescent display have all reached the stage of practical use, and the current goal can be said to be a high-density matrix type display.
マトリクス駆動に問題のある表示においては一能動付加
素子を用いた所謂「アクティブ・マトリクス」法が有効
である。For displays where matrix driving is problematic, a so-called "active matrix" method using one active additional element is effective.
表示装置に薄膜非線形抵抗素子を用いる事により、高密
度、高画質の表示が可能であり、薄膜非線形抵抗素子（
薄膜整流素子）が表示装置用能動付加素子として勝れて
いる事は前出願（特願昭５７−１６７９４５号）に記載
ずみである。さらに、薄膜非線形抵抗素子の駆動能力を
増すためには、薄膜非線形抵抗素子の閾値電圧（Ｖ，、
）を大きくする必要がある。この点についても前出願（
特願昭５７−１６７９４５号）に記載ずみである。By using thin-film nonlinear resistance elements in display devices, high-density, high-quality displays are possible.
The superiority of the thin film rectifying element as an active addition element for display devices has been described in a previous application (Japanese Patent Application No. 167945/1983). Furthermore, in order to increase the driving ability of the thin film nonlinear resistance element, the threshold voltage (V, ,
) needs to be increased. Regarding this point, the previous application (
It is described in Japanese Patent Application No. 167945/1983).
そこで本発明は一基板上に形成された電極群及び整流性
接続部から構成されて℃・る薄膜非線形抵抗素子におい
て、薄膜非線形素子を縦接続する際に生ずる逆整流性接
続部を短絡するために一逆整流性接−続部に金属アイラ
ンド層を導入するものである。金属アイランド層を導入
する事により、薄膜非線形抵抗素子に流せる電流量が太
き（でき、表示素子への電力供給量を大きくする事がで
きる。Therefore, the present invention aims to short-circuit the reverse rectifying connections that occur when vertically connecting the thin film nonlinear elements in a thin film nonlinear resistance element that is composed of an electrode group and a rectifying connection part formed on one substrate. In this method, a metal island layer is introduced at the one-way rectifying connection. By introducing the metal island layer, the amount of current that can be passed through the thin film nonlinear resistance element can be increased, and the amount of power supplied to the display element can be increased.
又−電流量或は耐圧のバラツキ等を減らす律ができる。Furthermore, it is possible to reduce variations in current amount or withstand voltage.
さらに−薄膜非線形素子は一表示の高密度化に伴い微細
素子化が要求される。Furthermore, thin film nonlinear elements are required to be miniaturized as display density increases.
そこで、短絡すべき金属層をアイランド化する事により
、金属層のエツチング時間を非常に短かくできたり或は
−アイランドの間隙からのエラチントの浸透により一金
属のエツチングなしに一半導体層のエツチングのみで薄
膜非線形素子の縦型接続ができる、金属層のエツチング
時間の短縮により素子劣化の防止、及びプロセスの短縮
化ができる。また、金属のエツチングが不要になる事に
より、プロセス的に簡単になり、素子も安定になる。以
下−図面に基づき本発明の詳細な説明する。Therefore, by forming the metal layer to be short-circuited into an island, the etching time for the metal layer can be extremely shortened, or - by permeation of elatint from the gap between the islands, only one semiconductor layer can be etched without etching one metal. This enables vertical connection of thin-film nonlinear elements, reduces the etching time of the metal layer, prevents element deterioration, and shortens the process. Furthermore, since metal etching is no longer necessary, the process becomes simpler and the device becomes more stable. In the following - the invention will be explained in detail with reference to the drawings.
第１図は一薄膜非線形抵抗素子の特性を示ず図である。FIG. 1 is a diagram that does not show the characteristics of a thin film nonlinear resistance element.
横軸は電圧■、縦軸し１電流ＩＬｆ′）ｌｏｇを取った
ものである。薄膜非線形抵抗素子を表示装置に利用する
場合の評価因子とじて−■。Ｆｌ、■１い Ｉ。Ｎがあ
る。良好な表示装置用非線形素子は、Ｉ ＯＦＦが十分
小さい事、Ｖ ｌｋが大きい事、Ｉ ＯＮが十分大きい
事である。The horizontal axis is the voltage (2), and the vertical axis is the current (ILf')log. Evaluation factors when using a thin film nonlinear resistance element in a display device -■. Fl, ■1 I. There is N. A good nonlinear element for a display device is such that I OFF is sufficiently small, V lk is large, and I ON is sufficiently large.
第２図に薄膜非線形抵抗素子の構造例を示す。FIG. 2 shows an example of the structure of a thin film nonlinear resistance element.
第２図において−１は基板、２は第１電極−６は半導体
層でＰ型、■型、Ｎ型半導体層より°構成されている。In FIG. 2, reference numeral -1 denotes a substrate, and reference numeral 2 denotes a first electrode 6, which is a semiconductor layer composed of P-type, ■-type, and N-type semiconductor layers.
、４は、層間絶縁膜−５は第２電極である。半導体層３
は、第１電極２とオーミック性を取るためのＰ型半導体
層及び第２電極５とオーミック性を取るためのＮ型半導
体層及び非線形抵抗接続部の一部であるＩ型半導体層か
ら構成されている。, 4, the interlayer insulating film-5 is the second electrode. semiconductor layer 3
is composed of a P-type semiconductor layer for obtaining ohmic properties with the first electrode 2, an N-type semiconductor layer for obtaining ohmic properties with the second electrode 5, and an I-type semiconductor layer that is part of the nonlinear resistance connection section. ing.
例として、ＰＩＮ型を示したが− ■型半導体層のない
ＰＮ型でも同様である、第３図は、第一２図の薄膜非線
形素子の整流接続部Ｐ Ｉ Ｎ接合を２段に重ねた構成
になっている。このＰＩＮ接合２段の整流部の等価回路
は第４図の如くである。つまり−１１と１６のＰ Ｉ
Ｎ接合間に逆整流接続部ＮＰ接合１２ができている。Although the PIN type is shown as an example, the same applies to the PN type without a type semiconductor layer. Figure 3 shows the rectifier connection part of the thin film nonlinear element shown in Figure 12, with the PIN junction stacked in two stages. It is configured. The equivalent circuit of this two-stage PIN junction rectifier is shown in FIG. In other words, -11 and 16 P I
A reverse rectification connection NP junction 12 is formed between the N junctions.
そのため、Ｉ ＯＮは減少し−かつ一不安定でバラツキ
の大きい素子になってしまう。第３図において−６が基
板、７が下層電極−８がＰＩＪＰＴＮＱ層整流部（半導
体層）、９が層間絶縁膜、１０が上層電極である。第４
図において、１１ばＰＩＮ接合部のダイオード、１２は
、ＮＰ接合部のダイオード−１３は−ＰＩＮ接合部のダ
イオードである。As a result, ION decreases and the device becomes unstable and has large variations. In FIG. 3, -6 is a substrate, 7 is a lower layer electrode, -8 is a PIJPTNQ layer rectifier (semiconductor layer), 9 is an interlayer insulating film, and 10 is an upper layer electrode. Fourth
In the figure, 11 is a diode at the PIN junction, 12 is a diode at the NP junction, and -13 is a diode at the -PIN junction.
以上の様に一単純に２層或は多層にしたのでは、ｉ Ｏ
Ｎが減少し表示素子の安定性が減少し、バラツギの大き
い素子になってしまう。If the structure is simply made into two layers or multiple layers as described above, i O
As N decreases, the stability of the display element decreases, resulting in an element with large variations.
そこで本発明では、第５図に示１〜如く、ＰＩＮ接合部
１７と１７の間のＮＰ接合部に金属アイランド層１８を
導入する事により、第６図の等価回路忙示されている如
（−２１及び２２０ＰＩＮ接合部のダイオードのみにな
る。金属層でなく金属アイランドであっても、アイラン
ド間隙の制御及び、アイランド層に接する層の低抵抗化
で十分コンタクトは取れる。Therefore, in the present invention, by introducing a metal island layer 18 into the NP junction between the PIN junctions 17 and 17 as shown in FIG. 5, the equivalent circuit shown in FIG. There are only diodes at the -21 and 220 PIN junctions.Even if it is not a metal layer but a metal island, sufficient contact can be made by controlling the island gap and lowering the resistance of the layer in contact with the island layer.
また、ＩＯＮを十分大きくしたまま、■１．が大きくで
き、素子バラツキをおさえ、表示素子の駆動を十分満足
し、均質な表示パネルが形成できる。Also, while keeping ION sufficiently large, ■1. can be made large, element variations can be suppressed, display elements can be driven satisfactorily, and a homogeneous display panel can be formed.
類似な構造素子として、光起電力素子：太陽電池がある
が一要求される特性及び構造が違っている。A similar structural element is a photovoltaic element (solar cell), but the required characteristics and structure are different.
特性的には、薄膜非線形素子が順方向バイアス（大電流
）動作させるのに対して、太陽電池は光により励起され
た電子及び正孔を電流として取り出すものである。その
ため太陽電池では一一般に短絡用の金属層或は導電層は
入れていない。栴造面でも、同様な事が言える、
つまり、太陽電池では、半導体層へ光が入射されなけれ
ばならない。そのため、少なくても片面ば、光が半導体
層へ入射する様に透明電極が使われる。これに対し一薄
膜非線形素子は、Ｉ ＯＦＦを極力小さくおさえなくて
はならない。そのため−半導体層へは極力光が入射され
ない様に半導体層の上下面を金属で覆い光マスクを形成
したり一半導体上へ光吸収層をもうけたり一或は、光起
電力を外部へ取り出さない様に薄膜非線形素子を２個リ
ング状に組み合せ、リング内で電流を消費させたりする
事が必要になる。太陽電池と薄膜非線形素子の構造は多
くの違った点を有している。Characteristically, while thin film nonlinear elements operate with a forward bias (large current), solar cells extract electrons and holes excited by light as current. Therefore, solar cells generally do not include a metal layer or conductive layer for short circuiting. The same thing can be said for the Senzo surface; in other words, in a solar cell, light must be incident on the semiconductor layer. Therefore, a transparent electrode is used on at least one side so that light can enter the semiconductor layer. On the other hand, in a thin film nonlinear element, I OFF must be kept as small as possible. Therefore, to prevent light from entering the semiconductor layer as much as possible, cover the top and bottom surfaces of the semiconductor layer with metal to form an optical mask, or create a light absorption layer on the semiconductor layer, or prevent the photovoltaic power from being extracted to the outside. Similarly, it is necessary to combine two thin film nonlinear elements in a ring shape and consume current within the ring. The structures of solar cells and thin film nonlinear devices have many differences.
つまり一太陽電池では一第３図の７或は１０の電極層が
透明であるのに対し、本発明の薄膜非線形抵抗素子は第
５図の構成から成っている。第５図において、１５が基
板、１６が下層電極−１７及び１７がＰＩＮ整流部（半
導体層）、１８が短絡用の金属アイランド層、１９が層
間絶縁膜、２０が上部電極である。第６図は、第５図の
等価回路であり２１及び２２がＰＩＮ接合部のダイオー
ドである。In other words, in one solar cell, the electrode layer 7 or 10 shown in FIG. 3 is transparent, whereas the thin film nonlinear resistance element of the present invention has the structure shown in FIG. 5. In FIG. 5, 15 is a substrate, 16 is a lower electrode, 17 is a PIN rectifier (semiconductor layer), 18 is a metal island layer for short circuiting, 19 is an interlayer insulating film, and 20 is an upper electrode. FIG. 6 is an equivalent circuit of FIG. 5, in which 21 and 22 are diodes at the PIN junction.
以上より明らかな如く、本発明は一基板上に形成された
電極群及び整流性接続部から成る薄膜非線形抵抗素子を
有する表示パネルにおいて一薄膜非線形抵抗素子を縦接
続する際に生ずる逆整流接続部を短絡するために一薄膜
非線形抵抗素子間に金属アイランド層をもうける事によ
り一 ■。Ｎを十分大きくしたまま− Ｖ ｌｈを大き
くてき一表示品質の向上ができる。As is clear from the above, the present invention relates to a reverse rectification connection that occurs when one thin film nonlinear resistance element is vertically connected in a display panel having a thin film nonlinear resistance element formed on one substrate and consisting of an electrode group and a rectification connection. ■By creating a metal island layer between two thin-film nonlinear resistance elements to short-circuit. Display quality can be improved by increasing -Vlh while keeping N sufficiently large.
さらに、薄膜非線形素子は一表示の高密度化に伴い微細
素子化が要求される。そこで、短絡すべき金属層をアイ
ランド化する事により一金属層のエツチング時間を非常
に短かくできたり或は、アイランドの間隙からのエツチ
ング液の浸透により、金属のエツチングなしに、半導体
１層のエツチングのみで薄膜非線形素子の縦型接続がで
きる。金属層のエツチング時間の短縮により素子劣化の
防止、及びプロセスの短縮化ができる。ま１こ、金属の
エツチングが不要になる事により−プロセス的に簡単に
なり一素子も安定になる。Furthermore, thin film nonlinear elements are required to be miniaturized as display density increases. Therefore, by making the metal layer to be shorted into an island, the etching time for one metal layer can be extremely shortened, or by allowing the etching solution to penetrate through the gap between the islands, one semiconductor layer can be etched without etching the metal. Vertical connections of thin film nonlinear elements can be made using only etching. By shortening the etching time of the metal layer, element deterioration can be prevented and the process can be shortened. First, by eliminating the need for metal etching, the process becomes simpler and each element becomes more stable.
以下に実施例を用いて本発明を説明する。The present invention will be explained below using Examples.
第７図は、半導体層がＰ型半導体層−Ｉ型半導体層−Ｎ
型半導体層から成るＰＩＮ接合の２層構造から成り、Ｉ
） Ｉ ＮとＰＩＮＯ間に金属アイランド層を形成した
２層薄膜非線形抵抗素子の製造工程を表わしている。FIG. 7 shows that the semiconductor layers are P-type semiconductor layer-I-type semiconductor layer-N
It consists of a two-layer structure of PIN junction consisting of a type semiconductor layer,
) The manufacturing process of a two-layer thin film nonlinear resistance element in which a metal island layer is formed between IN and PINO is shown.
第７図Ａは一基板６ｏ上へ透明電極層６１（表示電極層
）及び下層電極６２及び１層月のＰＩＮ型ダイオード層
３１３４．３５を形成した図である。第７図へにおいて
−６０はガラス或はセラミックス基板、６１は表示電極
層でＩＴＯ或は、ｓｎ’ｏ２或は薄膜金属膜である。６
２は下層電極でＣｒ或はＡｌ−Ｎｉであり、６２はＰ型
半導体層であり不純物としてＢ（ボロン）がドーピング
しであるアモーファス・シリコンである。ろ４は不純物
濃度の低い■型半導体層であり−アモーファス・シリコ
ン、６５はＮ型半導体層であり不純物としてＰ（リン）
がドーピングしであるアモーファス・シリコンでアル。FIG. 7A is a diagram in which a transparent electrode layer 61 (display electrode layer), a lower electrode layer 62, and a single-layer PIN type diode layer 3134.35 are formed on one substrate 6o. In FIG. 7, -60 is a glass or ceramic substrate, and 61 is a display electrode layer, which is ITO, sn'o2, or a thin metal film. 6
2 is a lower layer electrode made of Cr or Al--Ni, and 62 is a P-type semiconductor layer made of amorphous silicon doped with B (boron) as an impurity. 4 is a ■-type semiconductor layer with a low impurity concentration - amorphous silicon, and 65 is an N-type semiconductor layer containing P (phosphorus) as an impurity.
Al in amorphous silicon which is doped.
第７図Ｂは、１層口と２層目のＰＩＮダイオードの中間
層として金属アイランド層を形成した図である。形成法
としては金属膜を極めて薄く形成する場合−或は−１層
目のダイオードの最上層−Ｎ層表面を荒らし一金属の伺
着状態を変えたり一或は金属膜形成後エンチング又は、
ガス粒子でたたいたりする方法がある。材料としては、
Ａ／ｌＣｒ−Ｎｉ、’＋”、−ｔｘ、等である。第７図
Ｂにおいて３６が金属アイランド層である。FIG. 7B is a diagram in which a metal island layer is formed as an intermediate layer between the first layer and the second layer of PIN diodes. As for the formation method, if the metal film is to be formed extremely thinly, - or - the top layer of the first diode layer - the surface of the N layer may be roughened to change the adhesion state of the metal, or, alternatively, after the metal film is formed, it may be etched.
There is a method of hitting it with gas particles. As for the material,
A/lCr-Ni, '+'', -tx, etc. In FIG. 7B, 36 is a metal island layer.
第７図Ｃは一金属アイラノド層６６或は−ＰＩＮダイオ
ード上へ２層目のＰＩＮダイオードを形成した図である
。また−半導体層の安定化及び−エノチングーフォトリ
ゾグラフ工程による半導体層の劣化を防止するための金
属層も形成しである。第７図Ｃは第２層目のＰＩＮダイ
オード層を形成した図で６７がＰ型半導体層であり、６
８が■型半導体層−６９がＮ型半導体層であり−アモー
ファス・シリコンより成っている。４０は、半導体層の
安定化及びエツチング液フォトリゾグラフ工程による半
導体層の劣化を防止するための金属層（トップメタル層
）でＡｌ−Ｃｒである。FIG. 7C shows a second layer PIN diode formed on the monometallic island layer 66 or -PIN diode. In addition, a metal layer is also formed to stabilize the semiconductor layer and to prevent deterioration of the semiconductor layer due to the etching photolithography process. FIG. 7C is a diagram showing the formation of the second PIN diode layer, where 67 is a P-type semiconductor layer and 6
8 is a ■-type semiconductor layer, and 69 is an N-type semiconductor layer, which is made of amorphous silicon. Reference numeral 40 denotes a metal layer (top metal layer) made of Al-Cr for stabilizing the semiconductor layer and preventing deterioration of the semiconductor layer due to an etching solution photolithographic process.
第７図りは一第７図Ｃまでに形成された膜を所定の大き
さにパターニングした図である。この際、アモーファス
・シリコン層は反応性イオンエツチングでエツチングを
行ない、短絡用の金属アイランド層のエツチングは特に
行なわなυ・０第７図Ｅは本発明を用いて形成した薄膜
非線形抵抗素子である。第７図Ｅは、層間絶縁膜として
、Ｓ １（Ｊ２＋ Ｓ、＋３Ｎ、＋ポリイミド樹脂等を
形成した後に所定の所にコンタクトホールな形成し一配
線層としてＡｄ或ばＣｒを形成後、パターニングしたも
のである。第７図Ｅにおいて、４１が層間絶縁膜、４２
が配線層である。第７図Ｅの素子と各表示媒体を組み合
せる事により高＠５度で高品質の表示装置の形成ができ
る。Figure 7 is a diagram showing the film formed up to Figure 7C being patterned to a predetermined size. At this time, the amorphous silicon layer is etched by reactive ion etching, and the metal island layer for shorting is not particularly etched. . Figure 7E shows that after forming S1 (J2+ S, +3N, + polyimide resin, etc.) as an interlayer insulating film, contact holes were formed at predetermined locations, and after forming Ad or Cr as a wiring layer, patterning was performed. In FIG. 7E, 41 is an interlayer insulating film, and 42 is an interlayer insulating film.
is the wiring layer. By combining the element shown in FIG. 7E and each display medium, a high quality display device can be formed at a high @5 degree.
以上の如く一表示装置用多層薄膜非線形抵抗素子におい
て、多層に形成された薄膜非線形抵抗素子間に金属アイ
ランド層を形成する事により−１ＯＮを減少さぜる事な
く■１．が大きくでき、安定で経時変化の少ない多層薄
膜非線形抵抗素子の形成が可能となる。半導体層の形成
法は、プラズマＣＶＤ法のみならず、光ＣＶＤ法、スパ
ッタ法、蒸着法、イオンブレーティング法が有効である
。As described above, in a multilayer thin film nonlinear resistance element for a display device, by forming a metal island layer between the thin film nonlinear resistance elements formed in multiple layers, -1ON is not reduced.1. It becomes possible to form a multilayer thin film nonlinear resistance element that is stable and shows little change over time. Effective methods for forming the semiconductor layer include not only the plasma CVD method but also the photo CVD method, sputtering method, vapor deposition method, and ion blating method.
半導体の種類は−アモーファス・シリコン−微結晶シリ
コン−シリコンカーバイド−シリコンゲルマニウム−シ
リコンナイトライドがある。アモーファス・シリコンは
薄膜にもかかわらず価電子制御ができるため半導体とし
て格好の材料である。Types of semiconductors include - amorphous silicon - microcrystalline silicon - silicon carbide - silicon germanium - silicon nitride. Amorphous silicon is an ideal material for semiconductors because it can control valence electrons even though it is a thin film.
必要に応じてＢ−Ｐ＝ １−１− Ｎ＝ （Ｌ Ｃ，Ｇ
、、Ｓ ｎ−Ａｌ１− Ｌ ｌ−Ａ ｓ等を添加しても
よＵ−。BP= 1-1- N= (L C, G
,, S n-Al1- L l-A s etc. may be added.
第１図は、薄膜非線形抵抗素子の特性を示すグラフであ
る。第２図は、一般の１層薄膜非線形抵抗素子の構造を
示す断面図。第３図は、一般の２層薄膜非線形抵抗素子
の構造を示す断面図、第４図は第３図の等価回路図、第
５図は、本発明を用いた２層薄膜非線形抵抗素子の構造
を示す断面図、第６図は一第５図の等価回路図−第７図
は、本発明を用いた実施例の工程を示す断面図である。
Ｖ ｏ ｒ ｒ・・・・・・Ｉ ＯＦＦでの電圧、Ｖ
ＯＮ・・・・・ＩＯＮでの電圧−
１，６−１５，３０・・・・・・基板、６．８−１７＝
１７・・・・・・半導体層。
１８．３６・・・・・金属アイランド層。
第１図
ｙｏＦＦＶｔｈ ＶＯＮ
電圧（Ｖ）
第２図
り
λ
第７図
（Ｃ）
第７図
（Ｄ）
Ｊυ
（Ｅ）FIG. 1 is a graph showing the characteristics of a thin film nonlinear resistance element. FIG. 2 is a cross-sectional view showing the structure of a general single-layer thin film nonlinear resistance element. Fig. 3 is a cross-sectional view showing the structure of a general two-layer thin film nonlinear resistance element, Fig. 4 is an equivalent circuit diagram of Fig. 3, and Fig. 5 is a structure of a two-layer thin film nonlinear resistance element using the present invention. 6 is an equivalent circuit diagram of FIG. 5, and FIG. 7 is a sectional view showing steps of an embodiment using the present invention. V o r r...I Voltage at OFF, V
ON... Voltage at ION - 1,6-15,30... Board, 6.8-17=
17...Semiconductor layer. 18.36...Metal island layer. Fig. 1 yoFFVth VON Voltage (V) Fig. 2 λ Fig. 7 (C) Fig. 7 (D) Jυ (E)
Claims (1)
非線形素子を重ねて多層に形成し該薄膜非線形抵抗素子
の境界の半導体層間に金属アイランド層を形成した事を
特徴とする薄膜非線形抵抗素子。 （２）薄膜非線形抵抗素子は整流性接続部がＰＮ接合で
ある事を特徴とする特許請求の範囲第１項記載の薄膜非
線形抵抗素子。 （３）薄膜非線形抵抗素子は整流接続部がＰ型半導体層
とＮ型半導体層と、間に低不純物濃度の■型半導体層が
形成されている事を特徴とする特許請求の範囲第１項記
載の薄膜非線形抵抗素子。[Claims] (11) In a thin film nonlinear resistance element for a display device, one thin film nonlinear element is stacked to form a multilayer structure, and a metal island layer is formed between semiconductor layers at the boundary of the thin film nonlinear resistance element. Thin film nonlinear resistance element. (2) The thin film nonlinear resistance element according to claim 1, wherein the rectifying connection part of the thin film nonlinear resistance element is a PN junction. (3) The thin film nonlinear resistance element is characterized in that the rectifying connection part is a PN junction. 2. The thin film nonlinear resistance element according to claim 1, wherein the connection portion is formed between a P-type semiconductor layer and an N-type semiconductor layer, and a ■-type semiconductor layer with a low impurity concentration is formed between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11748983A JPS609177A (en) | 1983-06-29 | 1983-06-29 | Thin-film non-linear type resistance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11748983A JPS609177A (en) | 1983-06-29 | 1983-06-29 | Thin-film non-linear type resistance element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS609177A true JPS609177A (en) | 1985-01-18 |
Family
ID=14712983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11748983A Pending JPS609177A (en) | 1983-06-29 | 1983-06-29 | Thin-film non-linear type resistance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS609177A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6336542U (en) * | 1986-08-25 | 1988-03-09 | ||
| US5142331A (en) * | 1988-01-22 | 1992-08-25 | Mitsubishi Denki Kabushiki Kaisha | Photoelectric conversion semiconductor device |
| JPH0820955A (en) * | 1994-07-09 | 1996-01-23 | Nisshoku Corp | Inspection form for making slope form and slope form method by use thereof |
| JPH0820956A (en) * | 1994-07-09 | 1996-01-23 | Nisshoku Corp | Inspection form for making slope form and slope form method for use thereof |
| JPH0827801A (en) * | 1994-07-16 | 1996-01-30 | Nisshoku Corp | Frame body for slope frame formation and slope frame method using frame body |
| JPH08291524A (en) * | 1995-04-20 | 1996-11-05 | Koiwa Kanaami Kk | Spacer in form for slope frame |
-
1983
- 1983-06-29 JP JP11748983A patent/JPS609177A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6336542U (en) * | 1986-08-25 | 1988-03-09 | ||
| US5142331A (en) * | 1988-01-22 | 1992-08-25 | Mitsubishi Denki Kabushiki Kaisha | Photoelectric conversion semiconductor device |
| JPH0820955A (en) * | 1994-07-09 | 1996-01-23 | Nisshoku Corp | Inspection form for making slope form and slope form method by use thereof |
| JPH0820956A (en) * | 1994-07-09 | 1996-01-23 | Nisshoku Corp | Inspection form for making slope form and slope form method for use thereof |
| JPH0827801A (en) * | 1994-07-16 | 1996-01-30 | Nisshoku Corp | Frame body for slope frame formation and slope frame method using frame body |
| JPH08291524A (en) * | 1995-04-20 | 1996-11-05 | Koiwa Kanaami Kk | Spacer in form for slope frame |
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