JPS607183A - Manufacture of nonlinear resistor element - Google Patents
Manufacture of nonlinear resistor elementInfo
- Publication number
- JPS607183A JPS607183A JP58114982A JP11498283A JPS607183A JP S607183 A JPS607183 A JP S607183A JP 58114982 A JP58114982 A JP 58114982A JP 11498283 A JP11498283 A JP 11498283A JP S607183 A JPS607183 A JP S607183A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- layer
- electrode
- thin film
- nonlinear resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 93
- 239000010409 thin film Substances 0.000 claims abstract description 39
- 239000012535 impurity Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 239000010410 layer Substances 0.000 abstract description 109
- 239000002184 metal Substances 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910018725 Sn—Al Inorganic materials 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
Abstract
Description
【発明の詳細な説明】 用薄膜非線形抵抗素子の製造法に関する。[Detailed description of the invention] The present invention relates to a method of manufacturing a thin film nonlinear resistance element for use.
液晶、？，， ＥＣ− ＰＩ）Ｐ一蛍光表示等の各種表
示装置はいずれも実用化段階に達し、現在の目標は高密
度のマ） ＩＪクス型表示にあるといえる。liquid crystal,? Various display devices such as EC-PI)P-fluorescent displays have all reached the stage of practical use, and it can be said that the current goal is high-density MA)IJ type displays.
マトリクス駆動に問題のある表示方式の解決には能動付
加素子を用いた所謂「アクティブ・マトリクス」法が有
効であり，表示装置に薄膜非線形抵抗素子を用いる事に
よって、高密度、高画質の表示が可能であり、薄膜非線
形抵抗素子（薄膜整流素子）が表示装置用能動伺加素子
として勝れている事は前出願（特願昭５７−１６７９４
５号）に記載ずみである。The so-called "active matrix" method that uses active additive elements is effective in solving display systems that have problems with matrix drive. By using thin-film nonlinear resistance elements in the display device, high-density, high-quality displays can be achieved. This is possible, and the superiority of thin film nonlinear resistance elements (thin film rectifiers) as active additive elements for display devices was disclosed in the previous application (Japanese Patent Application No. 57-16794).
No. 5).
従来の能動素子としてはーセラミソクバリスタ（ Ｚｎ
Ｏ）或は、ＭＩＭ型ダイオードがあるが、バラツキ等が
あり、表示装置に利用する際多くの問題を有していた。As a conventional active element, the ceramic varistor (Zn
O) Alternatively, there are MIM type diodes, but they have variations and have many problems when used in display devices.
これに対し薄膜非線形抵抗素子は従来の問題を多くの点
で克服している。だが、薄膜非線形抵抗素子においても
、実際に表示装置に利用する場合、高温（約４００°Ｃ
）処理を通らなくてはならない。In contrast, thin film nonlinear resistance elements overcome many of the conventional problems. However, even in thin film nonlinear resistance elements, when actually used in display devices, high temperatures (approximately 400°C) are required.
) must go through the process.
そのため、熱処理を通す事により、経時変化を起こし、
表示装置の性能低下が起こり一非線形抵抗素子の耐熱性
向上及び安定化が要求される。そこで本発明は、第１電
極と、該電極上の半導体層と、該半導体層θ）第２電極
から成る薄膜非線形抵抗素子において、半導体層の形成
に伴い、半導体層の形成温度を下げてい（事を要旨とし
、耐熱性の向上及び、長期安定性の向上ができ、表示装
置の長期的な性能保持を可能とすることを目的とするも
のである。Therefore, by passing heat treatment, it will change over time,
As the performance of the display device deteriorates, it is required to improve the heat resistance and stabilize the nonlinear resistance element. Therefore, the present invention provides a thin film nonlinear resistance element consisting of a first electrode, a semiconductor layer on the electrode, and a second electrode (the semiconductor layer θ), in which the formation temperature of the semiconductor layer is lowered as the semiconductor layer is formed. The purpose of this invention is to improve heat resistance and long-term stability, and to maintain long-term performance of display devices.
以下１図面に基づき本発明の詳細な説明する。The present invention will be described in detail below based on one drawing.
第１図は一薄膜非線形抵抗素子の特性を示すグラフであ
る。横軸は電圧■、縦軸は電流■のｌｏｇを取ったもの
である、薄膜非線形抵抗素子を表示装置に利用する場合
の評価因子とじて− Ｉ。ＦＦ（非導通時の電流ＬＶ、
、（閾値電圧）−１゜Ｎ（導通時の電流）がある、良好
な表示装置用非線形抵抗素子とは、ｒｏＦ Ｆが十分率
さい事、■７．が犬さい事、Ｉ Ｏ１２が十分大きい事
である。FIG. 1 is a graph showing the characteristics of a thin film nonlinear resistance element. The horizontal axis is the voltage ■, and the vertical axis is the log of the current ■.I is an evaluation factor when using a thin film nonlinear resistance element in a display device. FF (current LV when non-conducting,
, (threshold voltage) -1°N (current when conducting) A good nonlinear resistance element for display devices is one in which the roF F is sufficiently high; ■7. is small, and IO12 is large enough.
第２図は一般的な薄膜非線形抵抗素子の構造例を示す断
面図である。第２図において、１は基板、２は第１電極
、６は半導体層、４は層間絶縁膜、５は第２電極である
。半導体層６は、第１電極２とオー ミック性を取るた
めのＰ型半導体層及び、第２電極５とオーミック性を取
るだめのＮ型半導体層及び、非線形抵抗接続部の一部で
ある■型半導体層から構成されている。FIG. 2 is a cross-sectional view showing an example of the structure of a general thin film nonlinear resistance element. In FIG. 2, 1 is a substrate, 2 is a first electrode, 6 is a semiconductor layer, 4 is an interlayer insulating film, and 5 is a second electrode. The semiconductor layer 6 is a P-type semiconductor layer for obtaining ohmic properties with the first electrode 2, an N-type semiconductor layer for obtaining ohmic properties with the second electrode 5, and a part of the nonlinear resistance connection section. It consists of a type semiconductor layer.
第３図は、第２図と異った一般的な構造例を示す断面図
である。第３図において、６は基板、７は第］電極、８
は半導体層、９は層間絶縁膜、１０は第２電極である。FIG. 3 is a sectional view showing a general structural example different from FIG. 2. In FIG. 3, 6 is the substrate, 7 is the electrode, and 8
9 is a semiconductor layer, 9 is an interlayer insulating film, and 10 is a second electrode.
半導体層８は、第１電極７とオーミック性を取るための
Ｐ型半導体層及び−第２電極１０と非線形抵抗接続する
Ｉ型半導体層から構成されて（・る。前記一般的な構造
例と類似な構造素子として、光起電力素子いわゆる太陽
電池があるが、要求される特性及び構造が違っている。The semiconductor layer 8 is composed of a P-type semiconductor layer for achieving ohmic properties with the first electrode 7 and an I-type semiconductor layer that is connected to the second electrode 10 with a nonlinear resistance. A similar structural element is a photovoltaic element, a so-called solar cell, but the required properties and structure are different.
特性的には、薄膜非線形抵抗素子が順方向バイアス（大
電流）動作させるのに対して一太陽電池は光により励起
された電子及び正孔を電流として取り出すもので゛ある
。Characteristically, a thin film nonlinear resistance element operates with a forward bias (large current), whereas a solar cell extracts electrons and holes excited by light as a current.
このため、要求される半纏体膜特性が違ってくる。第４
図に太陽電池の電流−電圧特性Ｊ）グラフを示す。Ｖ
ｏｃは開放端電圧、ｌｌＩＣは短絡電流である。実際に
は抵抗Ｒ６を接続し、ｙ ｍｐとＩ。、の積の電力が取
り出せるわけである。For this reason, the required properties of the hemi-coated film differ. Fourth
The figure shows a graph of current-voltage characteristics of solar cells. V
oc is an open circuit voltage, and llIC is a short circuit current. Actually, resistor R6 is connected, and ymp and I. Therefore, the power equal to the product of , can be extracted.
以上より、太陽電池の半導体層は、光励起キャリヤーを
できるだけ多く形成、つまり、光が効率よく半導体層で
吸収され、外部へ取り出される事が重要である。構造面
でも、同様な事が言える。From the above, it is important that the semiconductor layer of the solar cell forms as many photo-excited carriers as possible, that is, that light is efficiently absorbed in the semiconductor layer and taken out to the outside. The same thing can be said about the structure.
つまり、太陽電池では、半導体層へ光が入射されなげれ
ばならないため、少な（でも片面は一部が半導体層へ入
射する様に透明電極が使われる。In other words, in solar cells, since light must not be incident on the semiconductor layer, a transparent electrode is used so that only a small amount of light (but only a portion of it on one side) is incident on the semiconductor layer.
これに対し、薄膜非線形抵抗素子は、Ｉｏ□を極力小さ
くおさえなくてはならないため、半導体層へは極力光が
入射されない様に半導体層の上下面を金属で覆い光マス
クを形成したり、半導体上へ光吸収層をもうけたり、或
は、光起電力を外部へ取り出さない様に薄膜非線形素子
を２個リング状に組み合せ、リング内で電流を消費させ
たりする事が必要になる。以上のべたように太陽電池上
薄膜非線形抵抗素子の構造は多（の違った点を有（７て
いる。On the other hand, thin-film nonlinear resistance elements must keep Io□ as small as possible, so in order to prevent light from entering the semiconductor layer as much as possible, the upper and lower surfaces of the semiconductor layer are covered with metal, or an optical mask is formed. It is necessary to provide a light absorption layer on top, or to combine two thin film nonlinear elements in a ring shape so as not to extract the photovoltaic force to the outside, and to consume current within the ring. As mentioned above, the structure of thin film nonlinear resistance elements on solar cells has many different points.
また、太陽電池の場合、高密度化は実際上、太陽電池の
実効面積低下につながるため行なわれておらず、実際上
必要がない。そのため、ホトリンを数工程通し、微細素
子を形成する事はあまり行なわれていない。これに対し
、表示装置用の薄膜非線形抵抗素子は１表示の高密度化
に伴い、微細素子化が要求され、レジストのベーキング
或は。Furthermore, in the case of solar cells, densification is not actually carried out because it leads to a reduction in the effective area of the solar cell, and is not actually necessary. For this reason, it is not often done to form fine elements by passing photorin through several steps. On the other hand, thin film nonlinear resistance elements for display devices are required to be miniaturized as the density of one display increases, and resist baking or resist baking is required.
層間絶縁膜形成、表示部形成等長（の熱処理工程が必要
になる。A heat treatment process is required to form an interlayer insulating film and to form a display section.
そこで本発明は、半導体層を形成する際に、初期は高温
で形成し、膜の成長に伴って温度を随時低下させる事に
より、半導体層と第１電極との密着性が向上し、安定に
なり、半導体層の耐熱性が向」二１７、高温工程でも安
定になり一経時変化の少な（・良好な薄膜非線形抵抗素
子が形成できるようにした。半導体層が、Ｐ型半導体層
とＮ型半導体層から成る場合、或は、Ｐ型半導体層とＮ
型半導体層の間に低不純物濃度の■型半導体層を有する
場合に、従来の形成法では下層不純物層から上層形成時
に不純物が再拡散され不純物プロファイルが変わり一薄
膜非線形抵抗素子の■。２Ｆ の増加及び耐圧の減少−
Ｖ ｌｈのシフト等が起とり、表示用としての特性を満
足しなくなってしまう。Therefore, the present invention improves the adhesion between the semiconductor layer and the first electrode by forming the semiconductor layer at a high temperature initially and lowering the temperature as the film grows. This improves the heat resistance of the semiconductor layer, making it stable even in high-temperature processes, and exhibiting little change over time.A good thin-film nonlinear resistance element can be formed. When consisting of a semiconductor layer, or a P-type semiconductor layer and an N
When a type semiconductor layer with a low impurity concentration is formed between type semiconductor layers, in the conventional formation method, impurities are re-diffused from the lower impurity layer when forming the upper layer, changing the impurity profile. Increase in 2F and decrease in withstand voltage -
A shift in V lh occurs, and the characteristics for display purposes are no longer satisfied.
また、以後の熱処理に対しても不安定で、経時変化が太
き（、表示装置の性能低下をもたらす。Furthermore, it is unstable with respect to subsequent heat treatment, and changes over time (resulting in a decline in the performance of the display device).
これに対し本発明では、半導体層の第１層目を高温で形
成し、第２層目を温度を下げて形成する事により、第１
層の安定化及び再拡散の防止が促進され、半導体層の不
純物プロファイルを（ずす事なく薄膜非線形抵抗素子を
形成する事ができる。In contrast, in the present invention, the first layer of the semiconductor layer is formed at a high temperature, and the second layer is formed at a lower temperature.
Stabilization of the layer and prevention of rediffusion are promoted, and a thin film nonlinear resistance element can be formed without changing the impurity profile of the semiconductor layer.
なお薄膜非線形抵抗素子がアモーファスンリコンのＰ型
、■型−Ｎ型半導体層から成る場合−Ｐ及びＮ型半導体
層膜厚は、１層との非線形抵抗接合性のため、膜厚は薄
くても可能である。だが−Ｉ型半導体層は、耐圧及び耐
熱性、非線形抵抗性、安定性のために厚い膜（１００Å
以上）が必要である。そＪ）ため、■型半導体層形成時
間が、半導体層形成時間の大部分をしめ、上下不純物層
は短時間化できる。Note that when the thin film nonlinear resistance element is composed of amorphous silicon P-type, ■-type-N-type semiconductor layers, the film thickness of the P and N-type semiconductor layers is thin due to the nonlinear resistance bonding property with one layer. It is also possible. However, the I-type semiconductor layer is a thick film (100 Å
(above) are required. Therefore, the time required to form the ■-type semiconductor layer occupies most of the time required to form the semiconductor layer, and the time required to form the upper and lower impurity layers can be shortened.
又、■型半導体層の膜質が非線形抵抗素子の特性を左右
するため、良質の膜が必要である。そのため、形成速度
の低速化等が行なわれ、長時間化の傾向にある、そこで
第１層半導体膜を高温で形成し、不純物の結合状態を安
定化し、次に温度を下げ■型半導体層を形成する事によ
り、■型半導体層への不純物拡散が防止できる、次に最
上層半導体層を■型半導体層と同−或は低い温度で形成
スル事により、不純物プロファイルの整った、ＩｏＦ
Ｆが低（、Ｔ ＯＮは十分大きく、Ｖ ｌｈの大きな安
定な薄膜非線形抵抗素子の形成ができる。Furthermore, since the film quality of the ■-type semiconductor layer influences the characteristics of the nonlinear resistance element, a film of good quality is required. For this reason, the formation speed has been slowed down, and the time has tended to be longer. Therefore, the first layer semiconductor film is formed at a high temperature to stabilize the bonding state of impurities, and then the temperature is lowered to form a ■-type semiconductor layer. By forming the IoF layer, impurity diffusion into the ■-type semiconductor layer can be prevented. Next, by forming the topmost semiconductor layer at the same or lower temperature as the ■-type semiconductor layer, an IoF layer with a well-organized impurity profile can be formed.
A stable thin film nonlinear resistance element with a low F (T ON is sufficiently large and a large V lh) can be formed.
第３図に示した構造の素子、つまり一第１電極とオーミ
ック接続するための不純物層及び、第２電極と非オーミ
ツク接続するための低不純物層を有する半導体層から成
る非線形抵抗素子においても一不細物半導体層の形成温
度を高くし、低不純物層を不純物層より低温にする事に
より不純物の拡散が防止でき一不細物プロファイルをく
ずさずに安定かつ耐熱性のある薄膜非線形抵抗素子の形
成ができる。アモーファス・シリコンを利用する事によ
り大面積でバラツキの少ない素子が可能であり、不純物
イオンによるＰ或はＮ型制御も可能である。An element having the structure shown in FIG. 3, that is, a nonlinear resistance element consisting of a semiconductor layer having an impurity layer for ohmic connection with the first electrode and a low impurity layer for non-ohmic connection with the second electrode, also has the same structure. By raising the formation temperature of the impurity semiconductor layer and making the low impurity layer lower temperature than the impurity layer, diffusion of impurities can be prevented, and a stable and heat-resistant thin film nonlinear resistance element can be created without changing the impurity profile. Can be formed. By using amorphous silicon, devices with a large area and little variation are possible, and P or N type control using impurity ions is also possible.
以上より明らかな如く、本発明は、第１電極と、その上
に形成された半導体層、及び半導体層上の第２電極から
成る薄膜非線形抵抗素子において、半導体層の形成過程
に従い、半導体層の形成温度を下げていく事により、安
定で耐熱性のある、経時変化の少ない素子形成ができ、
表示装置の性能を長期間安定に保つ事ができる方法を提
供するものである。半導体層に不純物層を利用する際、
本発明により、不純物プロファイルをくずす事なく。As is clear from the above, the present invention provides a thin film nonlinear resistance element consisting of a first electrode, a semiconductor layer formed thereon, and a second electrode on the semiconductor layer. By lowering the formation temperature, it is possible to form elements that are stable, heat resistant, and have little change over time.
The present invention provides a method that can keep the performance of a display device stable for a long period of time. When using an impurity layer in a semiconductor layer,
With the present invention, the impurity profile remains unchanged.
Ｉｏ□を小さくおさえ、素子バラツキをなくし、耐圧向
上を行なう事ができる。It is possible to keep Io□ small, eliminate device variations, and improve breakdown voltage.
第５図Ａより第５図Ｉは、それぞれ半導体層がＰ型半導
体層、■型半導体層、Ｎ型半導体層からなる薄膜非線形
抵抗素子の製造工程を表わす断面図である。FIGS. 5A to 5I are cross-sectional views showing the manufacturing process of a thin film nonlinear resistance element whose semiconductor layers are respectively a P-type semiconductor layer, a ■-type semiconductor layer, and an N-type semiconductor layer.
第５図Ａは、基板−１−へ透明電極層（表示Ｎ極層）及
び第１電極を形成した図である。第５図へにおいて１１
はガラス或はセラミックス基板、１２は表示電極層でＩ
ＴＯ或は、ＳｎＯ２或は薄膜金属である、１３は第１電
極でＣｒ或はＡＩ或はＮ＋である。FIG. 5A is a diagram in which a transparent electrode layer (display N-pole layer) and a first electrode are formed on the substrate-1-. To Figure 5 11
1 is a glass or ceramic substrate, 12 is a display electrode layer I
The first electrode 13 is made of TO, SnO2, or a thin film metal, and is made of Cr, AI, or N+.
第５図Ｂは、第１電極１６上へＰ型半導体層を形成した
図である。第５図Ｂにおいて、１４がＰ型半導体層であ
り、不純物としてＢ（はう素）がドーピングしであるア
モーファス・シリコンであり、形成温度は約３００℃で
ある。FIG. 5B shows a P-type semiconductor layer formed on the first electrode 16. In FIG. 5B, 14 is a P-type semiconductor layer, which is amorphous silicon doped with B (boron) as an impurity, and the formation temperature is about 300°C.
第５図Ｃは、Ｐ型半導体層上へ不純物濃度の低いＩ型半
導体層を形成したものである。第５図Ｃにおいて１５が
Ｉ型半導体層であり、アモーファス・シリコン膜で、形
成時の温度を約２５０°Ｃで形成した膜である。In FIG. 5C, an I-type semiconductor layer with a low impurity concentration is formed on a P-type semiconductor layer. In FIG. 5C, 15 is an I-type semiconductor layer, which is an amorphous silicon film formed at a temperature of about 250°C.
第５図１〕は、■型半導体１５十へＮ型中導体層１６を
形成したものである。第５図りにおいて、１６がＮ型半
導体層であり、不純物としてｐ（ＩＪン）がドーピング
しであるアモーファス・シリコンである。形成温度は２
５０°Ｃ或は２００℃である、以上第５図へから第５図
りまでの工程により一第１電極上へ半導体層が形成され
た事になる。半導体層は、下側よりＰＩＮを例に示した
が、Ｎ Ｉ Ｐでも同様で゛あり、アモーファス・シリ
コンのみではなく微結晶シリコン、シリコンカーバイド
（Ｓ ｉ Ｃ： Ｈ）、シリコンナイトライド（Ｓ ｉ
Ｎ ： ｌ−１）、／リコンゲルマ（Ｓ ｔ Ｇ ｅ
： Ｈ）でも可能である。半導体形成法としては、プラ
ズマＣＶＤ法、光ＣＶＤ法、スパッタ法、蒸着法−イオ
ンブレーティング法が有効であり、ボーピング法として
は、ガス系からのドーピングを行なう。5], an N-type medium conductor layer 16 is formed on a ■-type semiconductor 150. In the fifth diagram, 16 is an N-type semiconductor layer, which is amorphous silicon doped with p (IJn) as an impurity. Formation temperature is 2
A semiconductor layer is formed on the first electrode by the steps from FIG. 5 to FIG. 5, which are performed at 50° C. or 200° C. As for the semiconductor layer, PIN is shown as an example from the bottom, but the same applies to NIP, and it is not only amorphous silicon but also microcrystalline silicon, silicon carbide (S i C: H), silicon nitride (S i
N: l-1), / recongerma (S t G e
:H) is also possible. As a semiconductor forming method, a plasma CVD method, a photo CVD method, a sputtering method, a vapor deposition method and an ion blating method are effective, and as a boping method, doping from a gas system is performed.
第５図ｒ＞ば、半導体層の安定化及び、エノチングーフ
ォ） ｌ）ソ工程による半導体層の劣化を防市するため
の金属層を形成した図である。第５図１うにおいて、１
７が金属層であり、ＡＩ或はＣｒ膜で゛ある。Figure 5 is a diagram showing the formation of a metal layer for stabilizing the semiconductor layer and preventing deterioration of the semiconductor layer due to the process. Figure 5, 1, 1
7 is a metal layer, which is an AI or Cr film.
第５図Ｆは、金属層１７と、半導体層１４．１５．１６
及び第２電極１９（光入射用マスク金属）をパターニン
グした図である、第５図Ｇは、透明電極１２をパターニ
ングし、表示電極部１２′を形成した図である。FIG. 5F shows the metal layer 17 and the semiconductor layer 14, 15, 16.
FIG. 5G, which is a diagram showing the patterning of the second electrode 19 (the mask metal for light incidence), is a diagram in which the transparent electrode 12 is patterned to form the display electrode portion 12'.
第５図１」は、層間絶縁層１８を形成し、所定の所・〜
相互接続用のコンタクトホールを形成した図である。第
５図１−１ ｖｃおいて、１８が層間絶縁層であり、Ｓ
ｉＯ□、Ｓｉ、Ｎ、−ポリイミド樹脂等である。In FIG. 5 1, an interlayer insulating layer 18 is formed and
FIG. 3 is a diagram showing contact holes for interconnection formed. In Figure 5 1-1 vc, 18 is an interlayer insulating layer, and S
iO□, Si, N, -polyimide resin, etc.
第５図１は、第２電極１９（相互配線層）を形成し、パ
ターニングした図である。薄膜非線形ｔＪｔ抗素子と表
示電極及び外部回路との相互配線を行なう事により一薄
膜非線形抵抗素子を有する表示基板を形成する事ができ
る。第５図１において−１９が第２電極で、Ａｌ或は、
Ｃ，である。第５図■と各表示媒体を組み合せる事によ
り、高密度で高画質の表示装置の形成ができる。FIG. 5 1 is a diagram showing the formation and patterning of the second electrode 19 (interconnection layer). A display substrate having a single thin film nonlinear resistance element can be formed by interconnecting the thin film nonlinear tJt resistance element, the display electrode, and an external circuit. In FIG. 5, -19 is the second electrode, which is made of Al or
C. A high-density, high-image-quality display device can be formed by combining each display medium as shown in FIG.
以上の如く、薄膜非線形抵抗素子の半導体層の形成時に
高温から低温へと温度を下げる事により、安定な半導体
層を得る事が可能となり、安定で経時変化の少ない薄膜
非線形抵抗素子の形成ができる。不純物をドーピングす
る場合は特に有効である。アモーファス・シリコンは、
薄膜にもかかわらず価電子制御ができるため、半導体層
として格好の材料である。必要に応じてＢ＝ Ｐ−１−
ｉ Ｎ、０、Ｃ，Ｇａ、Ｓｎ−Ａｌ、Ｌ＋−Ａｓ等を添
加してもよい。実施例では、各半導体層で階段状に温度
を下げたが、なだらかに時間に応じて温度を下げる事も
当然可能である。As described above, by lowering the temperature from a high temperature to a low temperature when forming the semiconductor layer of a thin film nonlinear resistance element, it is possible to obtain a stable semiconductor layer, and it is possible to form a stable thin film nonlinear resistance element with little change over time. . This is particularly effective when doping with impurities. Amorphous silicon is
Although it is a thin film, it can control valence electrons, making it an ideal material for semiconductor layers. B= P-1- as necessary
iN, 0, C, Ga, Sn-Al, L+-As, etc. may be added. In the embodiment, the temperature was lowered stepwise in each semiconductor layer, but it is of course also possible to lower the temperature gradually over time.
第１図は、薄膜非線形抵抗素子の特性を示すグラフ、第
２図は、半導体層が、Ｐ型、■型、Ｎ型半導体層から成
る一般的な薄膜非線形抵抗素子の構造を示す断面図、第
３図は、半導体層が、Ｐ型、■型半導体層から成る一般
的な薄膜非線形抵抗素子の構造を示す断面図、第４図は
、太陽電池の光照射下での特性を表わすグラフであり、
第５図Ａより第５図■はそれぞれ一半導体層がＰ型、■
型−Ｎ型よりなる本発明を用いた薄膜非線形抵抗素子の
実施例で、製造工程を説明するための断面図である。
ＶＯＦＦ ・・・・・・Ｌ Ｆ Ｆでの電圧、Ｖ ＯＮ
・・・・・ＩＯＮでの電圧、
１．６．１１・・・・・基板、
３．８・・・・・・半導体層、１６・・・・・・第１電
極、１４・・・・・・Ｐ型半導体層、１５・・・・・・
Ｉ型半導体層、１６・・・・・・Ｎ型半導体層、１９・
・・・・・第２電極。
瀉４１￥１
第５図
電圧〔ｖ〕
第５図
（Ｆ）
（Ｇ）
７FIG. 1 is a graph showing the characteristics of a thin film nonlinear resistance element, and FIG. 2 is a cross-sectional view showing the structure of a general thin film nonlinear resistance element in which the semiconductor layer is composed of P-type, ■-type, and N-type semiconductor layers. Figure 3 is a cross-sectional view showing the structure of a general thin-film nonlinear resistance element whose semiconductor layers are P-type and ■-type semiconductor layers, and Figure 4 is a graph showing the characteristics of a solar cell under light irradiation. can be,
From Figure 5A, Figure 5■ shows that one semiconductor layer is P type, and ■
FIG. 3 is a cross-sectional view for explaining the manufacturing process of an embodiment of a thin film nonlinear resistance element of type-N type using the present invention. VOFF ・・・・・・Voltage at LFF, VON
... Voltage at ION, 1.6.11 ... Substrate, 3.8 ... Semiconductor layer, 16 ... First electrode, 14 ... ...P-type semiconductor layer, 15...
I-type semiconductor layer, 16...N-type semiconductor layer, 19.
...Second electrode. 〉41￥1 Figure 5 Voltage [v] Figure 5 (F) (G) 7
Claims (5)
層上の第２電極から成る薄膜非線形抵抗素子において、
該半導体層の形成に伴い、半導体層の形成温度を、順次
下げる事を特徴とする薄膜非線形抵抗素子の製造法。(1) In a thin film nonlinear resistance element consisting of a first electrode, a semiconductor layer on the electrode, and a second electrode on the semiconductor layer,
A method for manufacturing a thin film nonlinear resistance element, characterized in that the temperature at which the semiconductor layer is formed is sequentially lowered as the semiconductor layer is formed.
る事を特徴とする特許請求の範囲第１項記載の薄膜非線
形抵抗素子の製造法。(2) The method for manufacturing a thin film nonlinear resistance element according to claim 1, wherein the semiconductor layer is comprised of a P-type semiconductor layer and an N-type semiconductor layer.
濃度のＩ型半導体層が形成されている事を特徴とする特
許請求の範囲第１項記載の薄膜非線形抵抗素子の製造法
。(3) Manufacturing a thin film nonlinear resistance element according to claim 1, characterized in that an I-type semiconductor layer with a low impurity concentration is formed between the P-type semiconductor layer and the N-type semiconductor layer. Law.
層の電気的接触が非オーミツク性である事を特徴とする
特許請求の範囲第１項記載の薄膜非線形抵抗素子の製造
法。(4) A method for manufacturing a thin film nonlinear resistance element according to claim 1, wherein the electrical contact between either the first electrode or the second electrode and the semiconductor layer is non-ohmic. .
特徴とする特許請求の範囲第１項記載の薄膜非線形抵抗
素子の製造法。(5) A method for manufacturing a thin film nonlinear resistance element according to claim 1, wherein the semiconductor layer is made of amorphous silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58114982A JPS607183A (en) | 1983-06-27 | 1983-06-27 | Manufacture of nonlinear resistor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58114982A JPS607183A (en) | 1983-06-27 | 1983-06-27 | Manufacture of nonlinear resistor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS607183A true JPS607183A (en) | 1985-01-14 |
Family
ID=14651418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58114982A Pending JPS607183A (en) | 1983-06-27 | 1983-06-27 | Manufacture of nonlinear resistor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607183A (en) |
-
1983
- 1983-06-27 JP JP58114982A patent/JPS607183A/en active Pending
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