JP2911291B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of forming a semiconductor device with less damage due to high temperature processing by shortening a high temperature processing time in a vapor phase growth method. It is about.

[0002]

2. Description of the Related Art A silicon solar cell will be described as an example of a conventional semiconductor device with reference to the drawings. FIG.
FIG. 1 is a cross-sectional view illustrating a schematic configuration of a conventional general solar cell. Referring to FIG. 5, on p-type crystal substrate 11, an n-type bonding layer 12 is formed. Thereby, the pn junction of the silicon solar cell is formed by the p-type crystal substrate 11 and the n-type junction layer 12. A passivation film 13 made of a silicon oxide film (SiO ₂ ) is formed on the n-type bonding layer 12. On this passivation film 13, a titanium oxide film (TiO ₂ )
An anti-reflection film 14 of light is formed. A surface electrode 15 made of Ag paste or the like is formed so as to penetrate the antireflection film 14 and the passivation film 13 and to be connected to the n-type bonding layer 12. On the other hand, on the back surface of the p-type crystal substrate 11, BSF
A (Back Surface Field) layer 16 is formed, and a back surface electrode 17 made of Al paste or the like is formed via the BSF layer 16.

Next, a method for manufacturing a conventional silicon solar cell having the above structure will be described. First, POCl
₃ Gas or PSG solution as a source of impurities
Phosphorus (P) is added to p-type crystal substrate 11
The n-type bonding layer 12 is formed by thermally diffusing the inside. Thereafter, by using a thermal oxidation method or the like on the n-type bonding layer 12, Si for reducing the recombination of carriers is formed.
A passivation film 13 such as O ₂ is formed. Then, on this passivation film 13, an antireflection film 14 for light such as TiO ₂ is formed. Thereafter, an Al paste is printed on the back surface of the p-type crystal substrate 11, and the BSF layer 16 is formed simultaneously with the formation of the back electrode 17 by firing the Al paste. Then, a predetermined pattern of Ag paste is printed on the anti-reflection film 14, and the Ag paste is printed.
The surface electrode 15 is formed by baking the paste.

[0004] A conventional silicon solar cell is formed through the above steps.
The high temperature thermal diffusion treatment during the formation of the bond can sometimes damage the substrate. That is, by performing the high-temperature treatment, crystal defects such as dislocations occur in the substrate. As a result, the characteristics of the formed element are impaired. Therefore, a method of forming a pn junction layer at a lower temperature than the thermal diffusion method has been studied in order to reduce damage to the substrate due to the high-temperature treatment described above.

[0005]

As described above, high-temperature processing in a semiconductor process sometimes causes loss of device characteristics. FIG. 6 shows an example of the configuration shown in FIG.
When a silicon solar cell is formed through a process in which thermal diffusion processing is performed at a high temperature of 0 ° C. (normal processing in the figure)
And a silicon solar cell (high-temperature treatment in the figure) formed through a process in which thermal diffusion treatment is performed at a temperature of 950 ° C. which is still higher than 850 ° C. FIG. Referring to FIG. 6, it can be seen that the spectral sensitivity characteristics of the solar cell subjected to the high-temperature treatment are remarkable in the long wavelength region and are inferior to the spectral sensitivity characteristics of the solar cell subjected to the normal treatment. That is, it is considered that the high-temperature treatment causes a crystal defect in the substrate, and thus such deterioration of the element characteristics is observed. Thus, if the heat diffusion temperature in the above-described normal processing can be further reduced, it is considered that the element characteristics are further improved.

Therefore, an attempt has been made to form the n-type junction layer 12 at a lower temperature by using a vapor phase growth method. The above-described n-type junction layer 1 in a semiconductor device
2 is formed, the impurity distribution of the n-type junction layer 12 is uniquely determined when the above-described thermal diffusion method is used. However, when the vapor deposition method is used, the impurity distribution can be freely adjusted. You can control. When forming a high-concentration n-type junction layer 12 in a crystalline silicon solar cell,
The entire n-type junction layer 12 is made to have a uniform high impurity concentration (hereinafter, referred to as “step doping” in this specification).
Rather, the element characteristics of the solar cell obtained are better when the impurity concentration in the n-type junction layer 12 is gradually increased from a low concentration to a high concentration (hereinafter, referred to as “gradient doping” in this specification). The results have been obtained.

[0007]

[Table 1]

Table 1 shows that the solar cell having the n-type junction layer 12 formed by the graded doping and the solar cell having the n-type junction layer 12 formed by the step doping. The results of comparing various element characteristic values with the battery are shown. In Table 1,
J _sc (mA / cm ² ) indicates the short-circuit current density,
V _OC (mV) indicates an open circuit voltage. Also, FF
Indicates a fill factor, and η (%) indicates a conversion efficiency. It can be said that the larger the values of these various characteristics are, the better the element characteristics are. Referring to Table 1, it can be seen that the device characteristics are better when the above gradient doping is performed.

In view of the above, when forming the n-type junction layer 12 by epitaxial growth using a vapor phase growth method, the concentration distribution of the n-type junction layer 12 is gradually changed. In this case, when the n-type bonding layer 12 is formed by the above-described vapor deposition method, the substrate temperature is an important film formation parameter. Then, depending on the conditions, there is a critical substrate temperature (hereinafter simply referred to as “critical temperature”) as to whether or not epitaxial growth occurs when various conditions other than the substrate temperature are kept constant. This critical temperature increases as the impurity concentration increases, due to the fact that crystal growth is hindered by the impurities taken in. Therefore, when forming the high-concentration n-type bonding layer 12, it is necessary to make the substrate temperature during deposition relatively high, although not as much as when performing thermal diffusion processing. Here, Table 2 shows experimental results on the possibility of crystal growth when using a PH ₃ gas as an impurity source and changing the flow rate of the impurity gas and the substrate temperature.

[0010]

[Table 2]

As shown in Table 2 above, it can be seen that the critical temperature is increased by increasing the impurity gas flow rate, that is, the impurity concentration. Therefore, in order to obtain a high carrier concentration layer similar to the n-type bonding layer 12 formed by the thermal diffusion method described in the conventional example, the substrate temperature must be set at 7 ° C.
It is considered necessary to set the temperature to about 50 to 850 ° C.
The temperature of 750 ° C. to 850 ° C. is lower than the processing temperature by the thermal diffusion method described in the conventional example, but is a temperature at which crystal defects can be sufficiently generated.

Therefore, in order to obtain a high carrier concentration layer comparable to that obtained by the conventional thermal diffusion method, the n-type bonding layer 12 must be formed.
During the deposition, a process was performed for about 30 to 60 minutes in a relatively high temperature atmosphere of 750 ° C. to 850 ° C. As described above, when the high-temperature treatment is performed for a relatively long time, there is a problem in that the element characteristics of the solar cell formed through this process are deteriorated.

[0013]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a second conductive type having a so-called inclined impurity concentration distribution in which an impurity concentration gradually changes on a first conductive type semiconductor substrate; It is assumed that the semiconductor layer is formed. Then, the temperature of the semiconductor substrate is changed in accordance with a change in the amount of gas containing the second conductivity type impurity in the atmospheric gas by using a vapor phase growth method, thereby forming the second conductivity type semiconductor layer. I do. The vapor phase growth method preferably comprises
This is an epitaxial growth method, and the temperature of the semiconductor substrate is favorable.
Preferably, at the critical temperature where epitaxial growth occurs
It is set based on a certain critical temperature.

[0014]

According to the present invention, the temperature of the semiconductor substrate is changed according to the change in the amount of the gas containing the second conductivity type impurity. The temperature of the substrate can be reduced. Accordingly, the temperature of the semiconductor substrate may be increased only when a portion having a high impurity concentration is formed in the second conductivity type semiconductor layer. That is, the high-temperature processing time can be shortened.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment according to the present invention will be described.
This will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a schematic configuration of a solar cell in one embodiment according to the present invention. Referring to FIG. 1, the configuration of this solar cell is substantially the same as that of the conventional example, and n-type bonding layer 2 is formed on one surface of p-type crystal substrate 1. A passivation film 3 is formed on the n-type bonding layer 2, and in this embodiment, the passivation film 3 also serves as a light reflection preventing film. A surface electrode 6 is formed so as to penetrate the passivation film 3 and be connected to the n-type bonding layer 2. On the other surface of the p-type crystal substrate 1, a back electrode 5 is formed via a BSF layer 4.

A method for manufacturing the solar cell having the above-described configuration will be described in detail below. First, the p-type crystal substrate 1
A p-type silicon single crystal wafer having a specific resistance of 4 Ω · cm, a plane orientation of <100> and a thickness of about 400 μm is used.
The p-type crystal substrate 1 has RCA cleaning and H
An oxide film removal process using F is performed. After that, the n-type bonding layer 2 is formed. In forming the n-type junction layer 2, M is performed by irradiating a silicon source with an electron beam.
BE (Molecular Beam Epitax)
y) is used.

The n-type bonding layer 2 has a thickness of about 1500 ° and is formed at a film forming rate of about 0.8 ° / s. The n-type impurities are generated by cracking (thermal decomposition) of the PH ₃ gas and are taken into the n-type junction layer 2. here,
The film forming speed is preferably a speed in the range of 0.1 ° / S to 10 ° / S. Further, the thickness of n-type bonding layer 2 is preferably in the range of 1000 to 5000 °. The PH ₃ gas flow rate is 0 to 3 in this embodiment.
cc. In this range of PH ₃ gas flow rate,
Since the impurity concentration in the n-type junction layer 2 has not reached saturation, it is considered that the PH ₃ gas flow rate and the concentration of the impurity (P) in the n-type junction layer 2 are almost proportional. And
At the time of the maximum flow rate of the PH ₃ gas (3 cc), the specific resistance of the n-type bonding layer 2 is taken in so as to be about 2-3 × 10 ⁻³ Ω · cm. On the other hand, the temperature of the p-type crystal substrate 1 is changed within the range of 500 to 750 ° C. according to the flow rate of the impurity gas.

Next, a method for controlling the temperature of the p-type crystal substrate 1 will be described.
An example will be described. Crystal epitaxial growth occurs
The critical temperature depends on the conditions, but other film forming conditions
If it is constant, the same manufacturing equipment
It is considered to be determined by temperature. Thereby, a certain PH_ThreeDark
Consider the critical temperature at which crystal growth occurs with respect to temperature
Can be Therefore, PH_ThreeFlow rate (impurities
(P) doping amount) F _PH3, Critical temperature for crystallization T
_epiIs experimentally measured. And these data
Is stored in a program such as a microcomputer.
Beforehand, PH_ThreeN while controlling the substrate temperature with respect to the flow rate
The mold bonding layer 2 can be formed.

The film forming speed at the time of forming the n-type bonding layer 2 is controlled to be substantially constant by a power controller linked to the film thickness monitor. For this reason, the film thickness is proportional to the film forming time, and the program is programmed based on the film forming time that is easy to control. Specifically, a table as shown in Table 3 is created by the microcomputer program.

[0020]

[Table 3]

Referring to Table 3 above, a certain film forming time t_X
(T₁, T_Two, ...), PH _ThreeFlow rate f_X(F₁,
f_Two, ...) and the substrate temperature T_X(T₁, T_Two,…)
Ram has been. As a result, the film forming time t_XAccording to the course of
For example, the film forming time is t₁In the case of_ThreeThe flow rate is
f₁And the substrate temperature is T₁Will be controlled by
You.

Here, referring to FIG._ThreeFlow rate
The method of controlling the substrate temperature will be described in more detail.
FIG._ThreeControls for flow rate and substrate temperature
It is a block diagram which shows a control system. Referring to FIG.
_ThreePH for controlling flow rate _ThreeFlow controller 8 and
Substrate temperature controller 9 for controlling the substrate temperature
Are connected to the microcomputer 7 respectively.
Has been continued. The microcomputer 7 has a tag.
The camera 10 is connected. With this timer 10,
Film formation time t_XControl. And by the timer 10
The obtained information is sent to the microcomputer 7.
You. Based on this information, the microcomputer 7
PH_ThreeFlow controller and substrate temperature controller 9
Is stored in the microcomputer 7 in advance.
Control according to grams. Thereby, PH_ThreeFlow rate and
And the substrate temperature is controlled.

It should be noted that the control error of the substrate temperature is considered to be about 10 ° C. in the apparatus for carrying out this embodiment. The set value of the substrate temperature is set to be about 15 ° C. higher than the measured value of the critical temperature.

Here, as shown in FIG.
Done PH_ThreeFlow rate, substrate temperature, deposition time and n-type bonding
The relationship between the thicknesses of the layers 2 will be described. Referring to FIG.
The film thickness of the n-type bonding layer 2 depends on the film forming time (t₁, T_Two,…)When
Both increase and increase to a film thickness of about 1500Å
I have. Then, the film forming time (t)₁, T_Two,…)
And PH_ThreeFlow rate (f₁, F_Two, ...) also changed
You. This film formation time and PH _ThreeThe relationship with the flow rate is shown in FIG.
This is indicated by a solid line. In addition, the film forming time (t ₁, T
_Two, ...) and PH_ThreeFlow rate (f₁, F_Two,…)
As shown by the dotted line in the figure, the substrate temperature (T₁,
T_Two, ...) are also changing. This substrate temperature is
As described above, based on the critical temperature for epitaxial growth,
Is set at a slightly higher temperature_Three
Controlled to keep the temperature relatively low when the flow rate is small
Is done.

As described above, when the PH ₃ flow rate is small, the substrate temperature is relatively lowered, and as the PH ₃ flow rate increases, the substrate temperature is raised. Therefore, the processing time at a high temperature can be remarkably shortened as compared with the related art, and damage in a substrate such as a lattice defect due to the high temperature processing can be significantly reduced. Thereby, it becomes possible to provide a solar cell having excellent element characteristics.

As described above, the n-type contact is formed on the p-type crystal substrate 1.
After forming the composite layer 2, a carrier is formed on the n-type bonding layer 2.
Of passivation film 3 to reduce recombination
I do. As the passivation film 3, a plasma C
Silicon nitride film (Si_ThreeN_Four) To form
Or SiO_TwoA membrane may be used. In this embodiment
In addition, the light reflection preventing film (ARC) also serves as
~ 700ÅSi _ThreeN_FourPassivation film 3
It is formed as. In addition, as an antireflection film, Ag
F_Two, Al_TwoO_Three, TiO_TwoOr the like may be used.

Next, an Al paste is printed on the back surface of the p-type crystal substrate 1 and the Al paste is baked to form the BSF layer 4 and the back electrode 5. And
A predetermined pattern of Ag is formed on the passivation film 3.
The paste is printed and the surface electrode 6 is formed by firing the Ag paste.

The spectral sensitivity characteristics of the solar cell manufactured through the above steps will be described with reference to FIG. FIG.
FIG. 4 is a diagram for comparing the spectral sensitivity characteristics of a solar cell manufactured according to the present invention with the spectral sensitivity characteristics of a solar cell manufactured through a conventional process. Referring to FIG. 4, a dotted line in the figure indicates a spectral sensitivity characteristic of a conventional solar cell subjected to a normal process, and a solid line in the figure indicates that the solar cell is manufactured based on the present invention. 4 shows spectral sensitivity characteristics of a solar cell. As shown in FIG. 4, it can be seen that the spectral sensitivity characteristic of the solar cell according to the present invention is remarkably superior in the long wavelength region to the spectral sensitivity characteristic of a solar cell manufactured through a conventional process. . That is, it is understood that the damage to the substrate is reduced and the long-wavelength sensitivity is improved by reducing the high-temperature processing time.

In the above embodiment, a solar cell has been described as an example of a semiconductor device. However, the present invention may be used for manufacturing a semiconductor device other than a solar cell, such as a light quantity sensor and a color sensor.

[0030]

As described above, according to the present invention, it is possible to shorten the high-temperature processing time when forming the second conductivity type semiconductor layer. Thus, damage such as crystal defects in the semiconductor substrate can be significantly reduced. This makes it possible to improve element characteristics such as long-wavelength sensitivity. That is, a higher performance semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of a solar cell in one embodiment according to the present invention.

FIG. 2 shows a substrate temperature, PH controlled according to the present invention.
FIG. 3 is a diagram showing an example of a control example of _three flow rates, film formation time, and film thickness of an n-type bonding layer.

FIG. 3 is a block diagram showing a schematic configuration of a control system based on the present invention.

FIG. 4 is a diagram comparing the spectral sensitivity characteristics of a solar cell manufactured according to the present invention and a solar cell manufactured using a conventional method.

FIG. 5 is a schematic sectional view showing an example of a conventional solar cell.

FIG. 6 compares the spectral sensitivity characteristics of a solar cell manufactured through a step of performing a high-temperature treatment (about 950 ° C.) in a conventional manufacturing method and a solar cell manufactured through a conventional normal step. FIG.

[Explanation of symbols]

Reference Signs List 1,11 p-type crystal substrate 2,12 n-type bonding layer 3,13 passivation film 4,16 BSF layer 5,17 back electrode 6,15 front electrode 7 microcomputer 8 PH ₃ flow controller 9 substrate temperature controller 10 timer 14 reflection Prevention film

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-184323 (JP, A) JP-A-63-40383 (JP, A) JP-A-2-202018 (JP, A) JP-A-2- 248038 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 31/04 H01L 21/205

Claims (2)

(57) [Claims] In a method of manufacturing a semiconductor device, a semiconductor layer of a second conductivity type having a variable impurity concentration is formed on a semiconductor substrate of a first conductivity type by a vapor phase growth method . A method of manufacturing a semiconductor device, comprising: forming the semiconductor layer by changing a temperature of the semiconductor substrate according to a change in a gas amount containing the second conductivity type impurity. 2. The method according to claim 1, wherein the vapor phase growth method comprises epitaxial growth.
Is the law, The temperature of the semiconductor substrate is such that epitaxial growth occurs.
Set based on the critical temperature, which is the critical temperature,
A method for manufacturing a semiconductor device according to claim 1.