JPS6091726A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To improve the high resolution and linearity by converting an input digital data into plural kinds of pulse width modulation waves and adding/synthesizing pulse width modulation waves within one converting period. CONSTITUTION:Input digital data converted into a parallel data at an S/P converter 2 is converted into 4 kinds of different pulse width control signals P1-P4 with a pulse width modulation circuit comprising an adder 5, complement circuits 6, 7, coincidence detection circuits 31-34, a counter 4, gate circuits 10, 20 and flip-flop circuits 51-54 or the like. A pulse width modulation output PWMout is outputted by controlling switches 71-74 of a modulation section 70 by the pulse width control signals P1-P4.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on PCM (Pulse-Code Mo
Regarding digital-to-analog conversion devices that are applied to various digital processing systems such as record players (duration), in particular pulse width modulation (PWM:
Pulse-Width Modulation)
It relates to a method that converts into waves and converts them into analogs.

[Background technology and its problems]

Conventional ↓Is it a digital signal in which each pictogram has a certain weight, like a simple binary code or a binary coded decimal code? A digital-to-analog (D/A) converter that converts into an analog signal is
Pulse amplitude modulation (PAM: Pulse A) corresponding to the digital information given by the weight of each bit above.
mplitude Modulation) waves and PW
A conversion system is widely known in which the digital signal is converted into an M wave, and the PAM wave or PW IvI wave is interpolated with a low-pass filter to obtain a cylindrical analog signal.

Digital signal' (zPAM wave conversion method (hereinafter referred to as P
It is called the AM method. ) D/A converters cannot in principle obtain conversion characteristics with good linearity, but they require a high-precision resistance adder circuit and current adder that accurately corresponds to the weight of each bit of the input digital signal. A circuit is required, and if the resolution is to be increased, the circuit scale must be large and the entire circuit must be made highly accurate. There is still a D/A method that converts digital signals into iPWM waves (hereinafter referred to as PWM method).
In the conversion device, the output pulse width can be controlled by a counter according to the input digital signal, so the circuit configuration is simple, but the conversion characteristics are in principle non-linear and include conversion errors, and the resolution is It is necessary to increase the operating frequency of the counter accordingly.

In other words, the analog signal converted by the PAM method and the PW
Comparing the analog signal converted using the M method, the first
PA that converted digital signals using each method as shown in the figure
Although both the M pulse and the PWM pulse have the same area, the duty ratio for the conversion period T does not change.
The PWM pulse whose duty to city changes with the M pulse matches the duty of the above PAM pulse at full-scale FS, and the closer the PWM pulse is to the OFS side, the closer the center t-F8 is.
, t-Lys LArs is the center t of the conversion period T
Because the distance from ψ is n, the instantaneous value level of each analog signal becomes lower in the PWM method than in the PAM method, as shown in Figure 2, and in the case of the PWM method, frequency modulation (FM: FrequencyModulati
on).

Note that when performing D/A conversion with N-bit resolution using the PAM method, for example, if a current addition circuit is used, N current sources that are weighted with high precision in accordance with the valley bits are required. shall be.

[Purpose of the invention]

Therefore, in view of the above-mentioned conventional problems, the present invention has been developed to
The object of the present invention is to provide a digital-to-analog converter with a novel configuration capable of performing high-resolution D/A conversion using the M method.

Furthermore, another object of the present invention is to
The aim is to improve the linearity of the conversion characteristics and to obtain analog signals with less distortion.

[Summary of the invention]

In order to achieve the above-mentioned object, the digital-to-analog converter according to the present invention converts input digital data into multiple types of pulse width modulated waves, adds and synthesizes each pulse width modulated wave within one conversion period, and performs left and right It is equipped with a pulse width modulation means for outputting a symmetrical synthesized pulse width modulated wave.

〔Example〕

Hereinafter, one embodiment of the digital-to-analog converter according to the present invention will be described in detail with reference to the drawings.In the embodiment shown in the pronk circuit diagram of FIG. Serial data of N points, which is a fully quantized analog signal, is supplied. In this embodiment, it is assumed that 3-bit serial data is supplied to the data input terminal 1.

The above serial data is supplied to the data input terminal 1, a color serial-to-parallel (S/P) converter 2, and the serial data Dp [Dψ, DI
, D2).

The device of this embodiment has a clock pulse φcL+c of a frequency of 9 fcLK supplied from a clock input terminal 3).
It is equipped with a 4-bit counter 4 that counts k, and by counting the above long pulse ψcLKk with the above-mentioned force 7 counter 4, each timing to, t□ . . .
・4-bit count output data Q+, Q2 obtained for each
, Q-, Q4's lower 3-bit data Qc[(h, Q
2-Q-) is supplied to the first gate circuit 10, and the first to fourth coincidence detection circuits 31, 32, 33, 3
It is supplied to 4 people.

The first gate circuit 10 includes an inverter 11 and a NOR
Constructed on Game Day 2.13, above counter 4
For nine 3-bit data Qc supplied from
OR gate 12 to 501 = Q1 + Q2 + possible.

The gate output signal Sa1 is output from the other NOR gate 13, and the second gate output signal Sc2 is output from the other NOR gate 13). The first gate output signal SG1 is supplied via the OR gate 41 to the cent input terminal of the first output terminal 51, and is also supplied via the OR gate 42 to the recent input terminal of the second output terminal 52. In addition, a second gate circuit formed in the first gate circuit 10 is
The gate output signal Sc2 is supplied to the second gate circuit 20 and also to the input terminal of the third flip 70 knob 53 and the input terminal of the fourth seven-ring front knob 54.

Further, the second gate circuit 2o is supplied with the most significant bit data Q4 of the counter/table, and is also supplied with carry output data C from the adder 5. This second gate circuit 2o is composed of an inverter 21 and AND gates 22 and 23, and one AND gate 22 outputs a third gate output signal 5ask, which is S aB "' S c2 ・C@Q4. At the same time, the other AND gate 23 outputs a fourth gate output signal 5ack of 5a4=Sa2.C.Q4.The third gate output signal 5ack formed by the second gate circuit 2o is
The gate output signal Sas is supplied to the cent input terminal of the first 7-ring flip-flop 51 via the OR gate 41i, and to the recent input terminal of the second flip-flop 52 via the OR gate 43. is supplied to.

Further, the fourth gate output signal SG4 formed by the second gate circuit 20 is supplied to the recent input terminal of the first flip-flop 51 via the OR gate 44, and It is applied to the recent input terminal of the second flip-flop 52 through the OR gate 42.

Furthermore, the adder 5 receives N (N=3) bit parallel data Dp[:Dψ] obtained by the S/P converter 2.
.
ψ+1 tD+ yD2 )) is supplied to the first coincidence detection circuit 10 and also to the first complement circuit 6. The first complement circuit 6 forms the complement 157'-Y5h of the addition output data DA and supplies this complement data Y5A-ff to the second coincidence detection circuit 32.

The operations of the adder circuit 5 and the first complement circuit 6 are shown in Table 1.

Table 1 also shows 9 N (N=3) obtained by the S/P converter 2
) Focus parallel data D p CDψ, Dl.

D2) is supplied to the third coincidence detection circuit 33 and also to the second complement circuit 7.

This second complement circuit 7 receives the parallel data D.

Two's complement data P of [Dψ=D1, D2] is formed, and this complement data is supplied to the fourth coincidence detection circuit 34.

The first coincidence detection circuit 31 compares the count output data Qc of the color/return 4 and the addition output data DA of the adder 5 to generate a negative result signal DPt.
'l: Supplied to the reset input terminal of the first flip-flop 51 via the OR gate 44. Further, the second coincidence detection circuit 32 compares the count output data Qc with the complement data 5A of the first complement circuit 6 and determines whether the negative number output signal? The signal is supplied to the cent input terminal of the second flip-flop 52 via the OR gate 43. Further, the third coincidence detection circuit 33 compares the count output data Qc with the parallel data Dpk from the S/P converter 2, and outputs a minus number output signal D.
P3 is supplied to the glue input terminal of the third 7-ring front panel 53.

The fourth coincidence detection circuit 34 collects the count output data Qc and the complement data Dpk of the second complement circuit 7.
Compare the - number configuration output signal DP.

All of the above are feeding the fourth Norimpflomp 540 cent input terminal.

The first to fourth flip-flops 51°52.5
3 and 54 are triggered at the rising timing of each signal supplied to the eaves top input terminal and the center input terminal, and send each positive output signal to the valley AND gates 61, 62,
63 and 64, the first to fourth pulse width control signals P1, P, .

Output PR,P.

The AND gates 61, 62, 63, and 64 are supplied with the most significant bit output Q4 of the counter 4 as a gate control signal via the inverter 60, and the most significant bit output Q4 becomes logic "0". - The gate is opened only during the first half period TA of the conversion period T. The first pulse width control is output from the first flip-flop 51 through the AND gate 61. The signal P1 is set by the first flip-flop 51 at the rising timing t4 of the first gate output signal Sa□, and is reset at the rising timing of the first digit output signal DP□. By the way, the above parallel data Dp
]: The pulse width τ1 changes as shown in FIG.

Further, the second flip-flop 5271-
The second pulse width control signal P2 outputted through the ND game (ND game) 61 is set by the second flip-flop 52 at the timing of the rise of the second digit output signal DP2, By resetting at the timing t4 of the rise of the gate output signal Sc1, the first pulse width control signal P is reset around the timing 44.
1, the pulse width τ2 changes symmetrically. Furthermore, the third pulse width control signal Ps and the fourth pulse width control signal P4 are connected to the parallel data D as shown in FIG.
According to p, the pulse width τ3 of the third pulse width control signal P3 changes from the rising timing of the second gate output signal SG2 to the timing ts7Q>7pj.
6...Changes in the order of tl.

The first to fourth pulse width control signals PlyP2
p P3 , P 4 are supplied to the modulation section 10 . n first to fourth switches 71, 72,
73, 74 and these switchers 1.72, 73, 7
first to fourth constant current sources 81, 82,
83.84 and each of the above switches 71, 72, 73.74
The above-mentioned valley constant current sources 81, 82, 83, 84 are connected to the inverting input terminal f' of the operational amplifier 90, and the operational amplifier 90 is connected between the output terminal 91 and the inverting input terminal 'i1. ．． and a feedback resistor 95. Note that the non-inverting input terminal of the operational amplifier 90 is grounded.

The first to fourth switches 71, 72, 73.74
are the first to fourth pulse width control signals P1. P
2 v P s −P4, four types of PWM waves P with different pulse width changing processes are generated according to the parallel data Dp.
W M s v P W IVI 2 , P W
Ms, PWM4k is formed and supplied to the inverting input terminal of the operational amplifier 900.

The operational amplifier 90 has each PWM wave PWM.

By adding and combining PWM2, PWMs, and PWM4, xQ1 outputs a left-right symmetrical PWM wave PWM OUT k within one conversion period T, as shown in FIG.

The PWM wave (PWIvll
scale], the pulse width is the maximum pulse width τ. 1
The wave corresponds to a PAM wave that does not include a PWM component in accordance with aX. Therefore, the PWM wave (PWMouT) is interpolated by a low-pass filter and exhibits a conversion characteristic that matches the A characteristic.
Is M 0UT) a conversion percentage in which the direction of the error due to left-right symmetry is reversed? will be presented. Moreover, the above PW
The IVI wave (P WMOUT) is generated by multiple constant current sources 81
, 82, 83, 84 current values II tI2 pIfi
Since the actual wave height value is determined by the average value of , ■,
The linearity of the conversion characteristics can be ensured without using high-precision constant current sources 81, 82, 83, and 84, and the device of this embodiment is suitable for being made into a monolithic IC.

In addition, in the above-mentioned embodiment, four constant current sources 81, 82,
4 types of PWM using 83 and 84 PWfvi1,
Since PWM2 tPWM8 and PWM4 are formed and 1 l 3 are added and combined, -FS, -FS, -FS4 2
4. The linearity of the conversion characteristic can be ensured in the FS, and this wave r can be obtained using M constant current sources.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, the digital-to-analog converter according to the present invention uses the PWM method to ensure excellent linearity and conversion rate, and achieves high resolution and high precision D.
/A conversion can be performed, and the intended purpose can be fully achieved.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram showing the PAM wave and I) WM wave basin generally used for D/A conversion.
FIG. 3 is a characteristic diagram comparing and showing valley conversion characteristics of D/A conversion using M waves and PWM waves. FIG. 3 is a pronk circuit diagram showing an embodiment of the digital-to-analog converter according to the present invention, FIG. 4 is a time chart showing the operation of the above embodiment, and FIG. ) waveform diagram of the PWM wave output from
The figure is a characteristic diagram showing the D/A conversion percentage of the above embodiment. 2... S/P converter winter... Color/return 5... Adder 6.7... Complement circuit TO, 20... e gate circuit 31. 32, 33, 34... - number Construction circuit 51.52
, 53, 54... Flip-flop 70... Modulation section 71.72, 73, 74... Switch 81, 82, 8
3.84... Constant current source 90... Operational amplifier patent applicant N21 Co., Ltd. agent Patent attorney Koike Mimuki 1) Sakae Mura - Procedural amendment (voluntary) August 71, 1980 Patent Office Director Manabu Shiga 1, Indication of the case 1982 Patent Application No. 199576 3, Relationship with the case of the person making the amendment Special r 2
18) Sony Corporation Name) Representative Norio Ohga 4, Agent 105 Voluntary 6, ``Detailed Description of the Invention'' column of the specification subject to amendment, Drawing 7, Contents of the amendment (7) -1,) from page 3, line 13 of the specification to page 1 of the same page
The statement on the 7th line, ``In order to separate, it includes...'' is corrected as follows. "To separate, frequency modulation (F" M: F'req
An error is generated due to ``uencyModulation''. In addition, as shown in Figure 2, the instantaneous value level of each analog signal converted by each method is higher in the PWM method than in the PAM method, and the conversion characteristics by the PWM method have non-linearity. I end up having it. (7-2) The statement ``Reset'' on page 7, line 19 of the specification is corrected to ``1-7 notes''. (7-3) The statement on page 10, line 12 of the specification “
Correct "-number output signal DP2" to "-number output signal DP2." (7-4) Statement on page 11, line 12 of the specification [
Departure Q and J are corrected as "Output Q and J." (7-5) The statement "[Timing 44"] on page 12, line 13 of the specification is corrected as "Timing 4t,"
(7-6) From page 14, line 10 of the specification to page 1 of the same page
The description in the first line r (P WMool is "(P
WM OUT ) is corrected. (7-7) Statement on page 14, line 15 of the specification (
-P W M OUT is "l' P W M OU
T) is corrected. (7-8) Statement 3 on page 14, line 17 of the specification ['-FSJ is corrected to l'-F'Sj. 4 (7-9) Statement on page 15, line 2 of the specification [-
Correct "concentration" to "dispersion". (7-10) The statement on page 15, line 3 of the specification “
Correct "distribution" to "concentration". (7-11) The statement "monochic" on page 15, line 12 of the specification is corrected to "monolithic." (7-12) The statement I"S FS I-1" on page 15, line 19 of the specification is corrected to I-HJ. (7-13) Figures 2, 5, and 6 of the drawings will be corrected as shown in the attached sheet. (7-14) As shown in red on the attached sheet, the instruction number 170 and its leader line are added to FIG. 3 of the drawing. Fig. 2 7Xη Pushtal No. 4b

Claims (1)

[Claims] A digital device that is equipped with a pulse width modulation means that converts all input digital data into multiple types of pulse width modulation waves, adds and synthesizes each pulse width modulation wave within one conversion period, and outputs a symmetrical composite pulse width modulation wave.・Analog converter.