JPS60100830A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To output repetitively each pulse width modulated wave within a conversion cycle and to improve the linearity of conversion, by using a means which converts the input digital data into the symmetrical pulse width modulated waves different in changing processes of pulse widths. CONSTITUTION:The quantized serial data DSR given from a data input terminal 11 are converted into parallel data D0-D2 by an S/P converter 12 and supplied to an conversion control part 10. The data D0-D2 are processed at the part 10 through a logical circuit containing complement circuits 31 and 32, a counter 42, coincidence circuits 51-54, FF61-63, an OR gate and an AND gate. The part 10 outputs a control pulse P0 obtained by compounding the control pulses symmetrical in change of pulse width. This pulse P0 is supplied to a modulation part 100 consisting of a switch 101, a constant current source 102 and an operational amplifier 103. Then data D0-D2 are converted into symmetrical pulse width modulated waves. These waves are outputted repetitively within a conversion cycle. This improves the linearity of conversion.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to PCM (Pulse-Code Mod
Regarding digital-to-analog conversion devices applied to various digital processing systems such as L/code players, in particular, digital data is converted to pulse width modulation (PW).
M: Pulse-Width Modulation
) Concerning the method of converting into waves and making them analog.

[Background technology and its problems]

Conventionally, digital-to-analog (D/A) converters convert digital signals in which each bit has a certain weight, such as simple binary codes or binary coded decimal codes, into analog signals.
Pulse amplitude modulation (PAM: Pulse A) corresponding to the digital information given by the weight of each bit above.
mplitude Modulation) waves and PW
A conversion method is widely known in which an analog signal is obtained by converting the digital signal into an M wave and interpolating the PAM wave or PWM wave using a low-pass filter.

A method of converting digital signals into PAM waves (hereinafter referred to as PAM
It is called a method. ) D/A converters can in principle obtain good conversion characteristics of positive and positive linearity, but they require a high-precision resistance adder circuit or current adder circuit that accurately corresponds to the weight of each bit of the input digital signal. In order to increase the resolution, the circuit scale becomes large and the entire circuit must be made highly accurate. In addition, in a D/A converter that converts a digital signal into a PWM wave (hereinafter referred to as the PWM method), the circuit configuration is simple because the output pulse width can be controlled by a counter according to the input digital signal. However, its conversion characteristics are in principle non-linear and include conversion errors, making it difficult to perform high-precision, high-resolution D/A conversion.

In other words, the analog signal converted by the PAM method and the PW
Comparing the analog signal converted using the M method, the first
PA that converted digital signals using each method as shown in the figure
The area of both the M pulse and the PWM pulse is the same, but the duty of the PWM pulse with respect to the conversion period T does not change.
The PWM pulse whose duty changes with respect to the M pulse has a duty matching with the above PAM pulse at full scale FS, and the PWM pulse on the OF'S side has a center tJ4.
Since F3 + ti, ... + t%s is far from the center of the modulation period T, the instantaneous level of each analog signal is lower (lower) in the PWM method than in the PAM method, as shown in Figure 2. , and in the case of the PWM method, frequency modulation (FM)
ion ).

[Purpose of the invention]

Therefore, in view of the above-mentioned conventional problems, the present invention has been developed by
The present invention provides a digital-to-analog converter with a new configuration that enables high-resolution D/A conversion using the WM method.

Another object of the present invention is to improve the linearity of D/A conversion characteristics using the PWM method and to obtain analog signals with less distortion.

[Summary of the invention]

In order to achieve the above-mentioned object, the digital-to-analog conversion device according to the present invention provides two types of pulse width control means for converting input digital data into left-right symmetrical pulse width modulated waves having different pulse width change processes. , and each pulse width modulated wave is alternately and repeatedly output within one conversion period.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital-to-analog conversion device according to the present invention will be described in detail below with reference to the drawings.

In the embodiment shown in the block diagram of FIG. 3, the data input terminal 11 is supplied with N-bit serial data DSR obtained by quantizing an analog signal at every sampling period Ts. In this embodiment, 3-bit serial data l
)sg is supplied to the data input terminal 11.

The serial data D8R is input to the data input terminal 11.
is supplied to the serial/parallel S/Pi converter 12 from
This 8/P converter 12 converts the data into parallel data Dp [ID, Jh, D2].

Parallel data DP obtained by the S/P converter 12
[Dgu, Dsummer, D2] are supplied to the modulation control section 10.

This modulation control section 10 includes a 5-bit counter 42 that counts clock pulses ψCLK having a frequency of fCLK that are supplied to a clock input terminal 41, and a 5-bit counter 42 that counts the clock pulses ψ that are supplied to a clock input terminal 41. 4th by counting LK
As shown in the figure, each timing t0゜1, . 1. ,...
・5-bit counting output data CQ, , Q
2. Q, ,Q, ,Q,) lower 4 bit data zQc[Q
1, Qz, Qa, Q4]
to fourth coincidence detection circuits 51, 52, 53, and 54 are provided.

The first coincidence detection circuit 51 includes the S/P converter 12
Parallel data Dp[DyJ.

D, , D2] are supplied, and 1-bit data Dsl of logic "0" is supplied from the first auxiliary data input terminal 21, and this 1-bit data Ds
The 4-bit data Dx [Dst, Dp, D+, Dz] obtained by adding t to the MSB side of the parallel data Dp and the count output data QC (Q, .

Q, , Q, , Q4] to detect a match. The coincidence detection output obtained by the first coincidence detection circuit 51 is supplied to the first flip-flop 61 as a reset pulse.

Further, the second coincidence detection circuit 52 is supplied with two's complement data DX of the 4-bit data Dp obtained by adding the 1-bit data Dsl to the parallel data DP from the first complement circuit 31, and this complement data DX is supplied from the first complement circuit 31. Dx and the count output data Qc are compared to detect a coincidence. The coincidence detection output obtained by the second coincidence detection circuit 52 is supplied to a second clip-flop 62 in the form of a set pulse.

Further, the third coincidence detection circuit 53 is supplied with the parallel data Dp obtained by the S/P converter 12, and receives 1-bit data of logic "1" from the second auxiliary data input terminal 22. D112 is supplied, and this 1-bit data Dsz is the M of the parallel data Dp.
4-bit data D y [DI, DI
, D2] and the count output data QC from the counter 42
[Q,,Q2. A match is detected by comparing Q=,Q, ].

The coincidence detection output obtained by the third coincidence detection circuit 53 is supplied to the third flip-flop 63 as a reset pulse.

Furthermore, the fourth coincidence detection circuit 54 converts the 1-bit data Ds2 of logic "1" into parallel data Dp.
The 2's complement data of the 4-bit data DY added to DY is supplied from the second complement circuit 32, and this complement data 4 is compared with the count output data Qc to detect a match. . The coincidence detection output obtained from the fourth coincidence detection circuit 54 is supplied to the third 7-lip-flop 63 as a set pulse.

The first flip-flop 61 is connected to the counter 42
The fourth bit data Q4 is supplied as a set pulse through the inverter γ1, and is set at the timing to (tla) shown in FIG. 4 by the set pulse. The first flip-flop 61 is reset by the coincidence detection output obtained from the first coincidence detection circuit 51, so that the first flip-flop 61 outputs the parallel data Dp CDp.

Di, D2] b (t17), tz (
The first control pulse P+ falling at each timing of ilg)', . . . h(tz3) is output.

Further, the second flip-flop 62 is supplied with a reset pulse from the inverter 71, and jx5(t3t ), t
o(taO) and t9(bs), and is reset by the above reset pulse at timing 116 (t3□) to output the second control pulse P2 as shown in FIG.

Each control pulse PI, P2 obtained by the first and second flip-flops 61 and 62 is supplied to a first AND gate 91 via a first OR gate 81.

Further, the third flip-flop 63 is connected to the fourth flip-flop 63.
The coincidence detection obtained by the coincidence detection circuit 54.

According to the above parallel data DP by output/output ([))
tz3. ((a) tz2,...(b) t17
(t9) tzs, (L+o) tzs, according to the parallel data Dp according to the coincidence detection output obtained by the third coincidence detection circuit 53.
-(t'5)ts+, the third control pulse P3 as shown in FIG. 4 is output.

This third control pulse P3 is applied to the second AND gate 92.
is supplied to.

The first AND gate 91 is supplied with the most significant beat data Q5 of the counter 42 as a gate control pulse via the inverter 72, and opens the gate during the period Ta from 1 to b6. and second control pulses Pl and P2 are supplied to the second OR gate 82.

Further, the second AND gate 92 is connected to the counter 4.
The most significant beat data Q5 of No. 2 is supplied as a gate control pulse, and the gate is opened during the period Tb from bs to tsz, and the third control pulse P3 is supplied to the second OR gate 82.

As shown in FIG. 4, the OR gate 82 generates a first control pulse Pl and a second control pulse P2 whose pulse widths change symmetrically around timing t8 in accordance with the parallel data Dp. The third control pulse P3, which is output during the period Ta and whose pulse width changes symmetrically around the timing t24, is output during the second period Tb, and the third control pulse P3 is output during the second period Tb, P2. A control pulse PG synthesized with P3 is supplied to the modulation section 100.

The modulation unit 100 includes a switch 101 whose switching is controlled by a control pulse Po supplied from the modulation control unit 1o, a constant current source 102 connected to the switch 101, and a constant current source 102 connected to the switch 101. 1(N
It is composed of an operational amplifier 103 connected to an inverting input terminal via an inverting input terminal, and a feedback resistor 105 connected between an output terminal 104 of this operational amplifier 103 and the inverting input terminal. Note that the non-inverting input terminal of the operational amplifier 103 is grounded.

The modulating section 100 has a switching control of the switch 101 by the control pulse Pa, so that the pulse width changes in the first period Ta and the second period Tb, and at each timing of t8 and t24, respectively. Two types of pulse width modulated waves PWM whose pulse widths change symmetrically according to the parallel data DP with WM as the center.
l, PWM 2 are output once within one conversion period T.

The pulse width modulated wave PWM outputted from the modulation section 100 during the first period Ta is composed of the first control pulse P1 and the second control pulse whose pulse width changes symmetrically with timing t8 as center node b. formed by pulse P2,
When interpolated with a low-pass filter and converted to an analog signal, the energy is distributed symmetrically around the above timing t8, so OFS and FS (full scale)
In between, the instantaneous value level is lower than the instantaneous value level of the PAM wave, and in the OFS and FS, the conversion characteristics shown by the dashed-dotted line in Fig. 5, which match the instantaneous value level of the PAM wave, are exhibited. . Further, the pulse width modulated wave PWM2 outputted during the second period Tb is symmetrical about the timing L24 and within the middle /D.
Since the energy is concentrated at , the conversion characteristic shown by the broken line in FIG. 5 is exhibited.

Therefore, as in this embodiment, there are two types of pulse width modulated waves PWM with different pulse width changing processes in the first period Ta and the second period Tb in one conversion period T.

By outputting PWM 2, conversion errors caused by the pulse width modulated waves PWM1 and PWM2 can be canceled out, and D/A conversion with excellent linearity can be performed.

Note that in the above embodiment, two types of pulse width modulated waves are
Although each pulse width modulated wave is output once during the conversion period T, each pulse width modulated wave may be alternately repeated and output multiple times within one conversion period T.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, the digital-to-analog converter according to the present invention has two types of pulse widths that have different pulse width changing processes and that change symmetrically depending on the input digital data. Since pulse width harmonics are output alternately within one conversion period, it is possible to cancel the conversion error that occurs in principle in the PWM method, and perform D/A conversion with excellent linearity, making it possible to achieve the intended purpose. can be fully achieved.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing PAM waves and PWM waves generally used for D/A conversion, and Fig. 2 shows a comparison of each conversion characteristic of D/A conversion using the above-mentioned PAM and PWM waves. It is a line diagram. FIG. 3 is a block circuit diagram showing an embodiment of the digital-to-analog converter according to the present invention, FIG. 4 is a time chart showing the operation of the above embodiment, and FIG. 5 is a conversion characteristic obtained by the above embodiment. FIG. 10... Modulation control section, 11... Theta input terminal, 3
1.32... Complement circuit, 42... Counter, 51,
52.53.54...-number construction circuit, 61, 62.6
3...Flip-flop, 81, 82-,, OL(
, gate, 91.92...AND gate, 100...
・Modulation section, 101...Switch, 102...Constant current source, 103...Operation amplifier, 104...Output terminal Patent applicant Sony Corporation representative Patent attorney Kodo Koike 1) Sakae Mura -

Claims (1)

[Claims] It is equipped with two types of pulse width control means for converting input digital data into left-right symmetrical pulse width modulated waves with different pulse width change processes, and is designed to alternately and repeatedly output each pulse width modulated wave within one conversion period. Digital to analog converter.