JP2689712B2 - PWM conversion circuit - Google Patents

Description

The present invention relates to a PWM conversion circuit, and more particularly to a PWM conversion circuit having an improved modulation method for obtaining its output.

[Conventional technology]

Conventionally, this type of PWM (pulse width modulation) conversion circuit has a circuit configuration that directly converts an input level into a pulse width.

FIGS. 4 (a) and 4 (b) are an output waveform diagram of the PWM conversion circuit and an input / output characteristic diagram of the output drive stage for explaining such a conventional example.

As shown in FIG. 4 (a), when the input data is 1, the output waveform in the conventional PWM conversion circuit is the output a in which the output distortion due to the load appears as errors B1 and B2, and the flat output B is supplied. ing.

Further, as shown in FIG. 4 (b), since the conventional PWM conversion circuit is a method of directly modulating the input level into the pulse width, when the level of the input data to be converted is small,
When the output level after PWM conversion is viewed in area, a non-linear region that is not proportional to the input level occurs.

FIG. 5 is a detailed waveform diagram of the conversion output shown in FIGS. 4 (a) and 4 (b).

As shown in FIG. 5, the waveform c in the drive stage is different from the PWM output waveform a in the conventional PWM output system due to the weight of the load and the drive capability of the drive stage. "Dullness" occurs, and because of this, PWM
The output waveform a and the drive stage waveform c no longer have a linear proportional relationship.

Generally, the time dulling at the rising and falling parts,
That is, assuming that the generation time is t and the length of the PWM output waveform a is T, the output power (area) “D” in the driver stage has a relationship of D = {f (t) + (T−t)} A. . This is as shown in FIG. 4 (b) described above.
This shows that nonlinearity occurs in the short area of the PWM output waveform. It should be noted that f (t) is a function representing the nonlinear portion at the rising and falling edges with respect to time t, and A is the gain at the driver stage.

[Problems to be solved by the invention]

The conventional PWM conversion circuit described above uses a method that directly modulates the input level into a pulse width, so if the input level to be converted is small, the output after PWM conversion is The disadvantage is that the level is no longer proportional to the input level.

An object of the present invention is to provide a PWM conversion circuit that prevents non-linearity due to the difference in load after the PWM output stage.

[Means for solving the problem]

The PWM conversion circuit of the present invention includes an addition circuit that adds predetermined offset data to latched input data, a counter circuit that is reset by a conversion start signal and starts a clock counting operation, a count value of the counter circuit, and the addition circuit. On the basis of the output of the counter circuit, a comparison circuit that compares the addition results of the first flip-flop that is reset by the conversion start signal and that supplies a positive-side conversion output and that is reset by the coincidence output of the comparison circuit. A decoder for generating a first decode signal and a second decode signal for controlling the counter circuit, and a second flip-flop set by the coincidence output of the comparison circuit and reset by the second decode signal of the decoder. And the output of the second flip-flop causes an error in the adder circuit. An offset generation register for generating set data, a delay shift register for performing delay control of the LSB of the latched input data by the coincidence output of the clock and the comparator, a delay output of the delay shift register and the second And a third flip-flop that is set based on the output of the flip-flop and supplies the negative side conversion output and is reset by the second decode signal of the decoder, and the operation of the offset data and the adder circuit and the like. When obtaining a desired output level by the pulse width of the bias pulse of a constant length obtained by the first output pulse converted into the sum of the pulse width of the bias pulse and the pulse width proportional to the input, A second output pattern of opposite polarity obtained by the same operation as the first output pulse. Create a scan, configured to form a PWM output by the difference of the pulse width of the first and second output pulses.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a PWM conversion circuit diagram showing an embodiment of the present invention.

As shown in FIG. 1, in this embodiment, 8-bit data is input from the data input terminal 2 to the data input latch 9, and a PWM conversion start signal is input from the PWM conversion start signal input terminal 1. This conversion start signal resets the counter 6 via the OR gate 16 and starts the counting operation of the clock input 3. Further, the adder 8 has a data input latch 9
The 7-bit offset data supplied from the offset generation register 17 and the 7-bit offset data from
The 8-bit output which is the addition result of the adder 8 and the value of the counter 6 are compared by the comparator 7, and the set / reset flip-flop (F / F) 14 is reset by the result. Since this F / F14 is set by the PWM conversion start signal from the input terminal 1, the input signal + from the PWM positive side output terminal 4
The output of the pulse width for the offset is obtained.

On the other hand, the decoder 10 is for determining the length of one cycle of PWM conversion. For example, if the length of one cycle at this time is N clocks, this decode signal is output to the signal line X. The other output of the decoder 10 has the maximum value of the input data as M, the offset value as ΔN, the delay time in the delay shift register 12 and the fall detection circuit as F (K), PW.
When the pulse output interval of the M positive side output terminal 4 and the PWM negative side output terminal 5 is ΔK, a value obtained by decoding (M / 2 + 2ΔN + ΔK) is output to the signal line Y.

Furthermore, the data input from the data input terminal 2 is 2 '
If it is an S complement binary code, the data value taken in by the data input latch 9 is shifted by 1 bit on the output wiring so as to be halved. At the same time, the MSB output of the data input latch 9 is inverted and converted into an offset binary code. At this time, LSB lost by 1/2 operation
1 bit is used as the delay control signal 13 to the delay shift register 12, and the delay control for only one clock is performed in synchronization with the clock from the clock input terminal 3. That is, the pulse width of the PWM negative side output terminal 5 is controlled to be reduced by one clock depending on the odd / even number of the input data. This means that the delay time F (K) described above is "1" or "0".
This means that only one of the clock values can be taken. The output of the offset generation register 17 outputs two kinds of values by the output of the set / reset flip-flop 11.

In addition, the PWM positive side output terminal 4 and the PWM negative side output terminal 5 are
The subtraction circuit 22 is connected to the subtraction amplifier 21 via LPFs 19 and 20.

Next, the present embodiment will be described in detail by setting specific numerical values for the above-mentioned temporary variables M, ΔN, N and ΔK.

First, assuming that M = 256, ΔN = 16, N = 192, ΔK = 16 and the input data is “00”, the input data “00” is offset binary by the data input latch 9, that is, halved. , 40H is input to the adder 8. Adder 8
Is the value output from the offset generation register 17 Is added to give 50H (80). A pulse of this length is P
Output from the WM positive output terminal 4.

Next, the value of the offset generation register 17 is changed by the output from the set / reset F / F11. And the 7-bit data "40H" output from the input data latch 9 is added by the adder 8. As a result, the comparator 7 outputs a coincidence signal when the counter 6 reaches 70H, so the set / reset F / F1
Set 1. At this time, since the LSB of the 1-bit data output from the data input latch 9 is “0”, F
(K) becomes "0".

Next, the count value of the counter 6 When it becomes, reset the set / reset F / F15.
Therefore, as a result, (B0H-70
H) = 50H length pulse is output.

Similarly, the output pulse width from the PWM output terminals 4 and 5 depending on the value of the input data is as shown in Table 1 below.

Becomes

 FIG. 2 is a PWM conversion output waveform diagram in FIG.

As shown in FIG. 2, the output waveform a at the positive side output terminal 4 is a waveform when the input data is 1 and the offset is 4, and the output waveform b at the negative side output terminal 5 is the input data is 0 and the offset is 4. Is a waveform when 4 is set. These output waveforms a and b both have output strains A1 to A4 due to the load, but the output waveform (ab) represented by the area is strain A1.
~ Waveform without A4. This is clearly an improvement when compared with FIGS. 4 and 5 described above.

It should be noted that the output (ab) in FIG. 2 does not represent a differential output when the outputs a and b in the figure are the same on the time axis, and does not represent the area of the output a and the area of the output b. The difference is expressed in the same height as the two outputs a and b. Therefore, it is shown that a correct area can be obtained even at the PWM output minimum value by adding a constant offset pulse width to the two outputs a and b.

In short, according to the present embodiment, two sets of PWM outputs are output, the output pulse is given a time offset, and the output level is configured by the difference between them, thereby eliminating the nonlinear output in the minute level conversion. be able to.

FIG. 3 is an application circuit diagram using the PWM conversion circuit of the present invention.

As shown in FIG. 3, such an application circuit connects the coils L1 and L2 to the PWM conversion circuit 23 of the present invention through power drivers 24 and 25, and combines them with capacitors C1 and C2 to form a low-pass filter. This low-pass filter is for removing the carrier of the PWM output. In this application example,
The carrier of the output of the PWM conversion circuit 23 is removed by a filter composed of a coil and a capacitor, and the load 26 is directly driven by the removed output. Therefore, the subtraction amplifier 21 in the subtraction circuit 22 of the above-described embodiment is not necessary. In addition, there is an advantage that power efficiency can be improved.

〔The invention's effect〕

As described above, the PWM conversion circuit of the present invention adds a temporal offset to the conversion output and decomposes the input data into two sets of data having different polarities, and obtains the temporal offset obtained by the above method. By obtaining the difference between the two sets of PWM outputs, the effect is that it is possible to suppress the non-linearity due to the difference in load after the PWM output stage in the minute level conversion.

[Brief description of the drawings]

FIG. 1 is a PWM conversion circuit diagram showing an embodiment of the present invention, and FIG.
The figure is a PWM conversion output waveform diagram in FIG. 1, FIG. 3 is an application circuit diagram using the PWM conversion circuit of the present invention, FIG. 4 (a),
(B) is an output waveform diagram of a PWM conversion circuit and an input / output characteristic diagram of an output drive stage for explaining an example of the conventional example, and FIG. 5 is a detailed description of the conversion output shown in (a) and (b) of FIG. It is a waveform diagram. 1 ... PWM conversion start signal input terminal, 2 ... data input terminal, 3 ... clock input terminal, 4 ... PWM positive side output terminal, 5 ... PWM negative side output terminal, 6 ... counter, 7 ...
Comparator, 8 ... Adder, 9 ... Data input latch, 10 ...
… Decoder, 11,14,15 …… Set / reset flip-flop (F / F), 12 …… Delay shift register, 13 ……
Shift register control signal for delay, 16 ... OR gate,
17 ... Offset generation register, 18 ... AND gate, 19, 20 ... Low-pass filter (LPF), 21 ... Subtraction amplifier.

Claims (1)

(57) [Claims] 1. An adder circuit for adding a predetermined offset data to latched input data, a counter circuit reset by a conversion start signal to start a clock counting operation, a count value of the counter circuit and an addition result of the adder circuit. A first flip-flop that is reset by the conversion start signal and supplies a positive side conversion output and is reset by the coincidence output of the comparison circuit; and the counter circuit based on the output of the counter circuit. A decoder for creating a first decode signal and a second decode signal for controlling, and a second flip-flop that is set by the coincidence output of the comparison circuit and is reset by the second decode signal of the decoder,
An offset generation register that creates offset data in the adder circuit by the output of the second flip-flop, and a delay shift register that performs delay control of the LSB of the latched input data by the coincidence output of the clock and the comparator. And a third flip-flop which is set based on the delay output of the delay shift register and the output of the second flip-flop and which supplies a negative-side conversion output and is reset by the second decode signal of the decoder. In order to obtain a desired output level from the offset data and the pulse width of the bias pulse of a constant length obtained by the operation of the adder circuit, etc., a pulse width proportional to the pulse width of the bias pulse and the input A first output pulse converted to a sum of lengths, and A second output pulse of opposite polarity obtained by the same operation as the output pulse of the, and PWM conversion characterized by forming a PWM output by the difference in the pulse width of the first and second output pulse circuit.