JPS6198024A - Digital to analog converter - Google Patents

Abstract

PURPOSE:To obtain a digital-analog converter high in resolution and superior in linearity by converting high-order digit bits on PAM basis and low-order digit bits on PWM basis, and combining them. CONSTITUTION:Five-bit data D0-D4 are inputted to an S/P converter 2; the low-order two digit bit data D2-D4 are supplied to a PWM control part 20, and the high-order two digit bit data D0 and D1 are supplied to a PAM control part 30. Signals from the PWM control part 20 and PAM control part 30 are inputted to a modulation part 40 and an output switch circuit 42 is controlled by the current source 41 consisting of eight constant current sources (a)-(h) which are equal in current value, so that an analog signal output equal to the input data is obtained from an inverting amplifier circuit 54. Then, the eight constant current sources (a)-(h) are used equally to suppress the influence of variance among the current sources upon the linearity.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital-to-analog converter (hereinafter referred to as a D/A converter) that converts a digital signal encoded by binary weighting into an analog signal. ), in particular, the input digital data is converted into a pulse amplitude modulated wave (Pulse amplitude modulated wave).
Amplitude Modulation.

Hereinafter, it will be referred to as a PAM wave. ) and pulse width modulated wave (Pulse
Width Modulation, hereinafter referred to as PWM wave. ) and converts it into analog.

The D/A conversion device according to the present invention is, for example, a so-called P
CM (Pulse Code Modulation
) :applies to t-dio, etc.

[Conventional technology]

Conventionally, D/A converters that convert digital signals, such as simple binary codes and binary coded decimal codes, in which each bit has a certain weight into an all-analog signal, convert digital information given by the weight of each bit. PAM wave and PW corresponding to
A conversion method is widely known in which an analog signal is obtained by converting the digital signal into M# and interpolating the signal through the PAM wave or PWM wave all low-pass filter.

A method of converting digital signals to kPAM waves (hereinafter referred to as PAM
In principle, the D/A converter of this method can obtain conversion characteristics with good linearity. If a complete adder circuit is required and the resolution is to be increased, the circuit scale will increase, and the entire circuit must be formed with high precision.Furthermore, in order to perform D/A conversion with a resolution of N pits using the PAM method, For example, if the entire current addition circuit is used, N constant current sources weighted with high precision are required for each pit.

The conventional technology for weighting the constant current sources is as follows:
For example, a current distribution device described in Japanese Patent Publication No. 57-31809 is known.

In addition, there is a method for converting digital signals to kPWM waves (hereinafter referred to as
It is written as PWM method. )'s D/A converter has a simple circuit configuration because the output pulse width can be controlled by a counter according to the input digital data, but its conversion characteristics are in principle non-linear and include conversion errors. Furthermore, it is necessary to increase the operating frequency of the counter depending on the resolution.

In other words, when the same person's data is D/A converted using the ePAM method and the PWM method, the PA for the same person's data is
As shown in Figure 4, the M wave and PWM wave have the same time integral value, but the PWM wave with changing pulse width has an input other than zero or full scale (FS) that matches the PAM wave with changing pulse height. In the data, the signal energy is more concentrated at the sample points than in the above PAM wave, so the instantaneous value novelty when converted into an analog signal by interpolation with a low-pass filter etc. is higher, and in the PWM method, as shown in Figure 5. This results in non-linear conversion characteristics.

The nonlinearity of the conversion characteristic in the PWM method changes depending on the frequency of the analog signal, and the higher the signal frequency, the greater the distortion due to the nonlinearity.
The larger the maximum pulse width of the PWM wave within, the larger the above-mentioned type becomes.

To reduce the conversion distortion in the above PWM method, pWM
The pulse width of the PWM wave indicating the ILSB of data may be reduced by increasing the operating frequency of the counter that controls the pulse width of the wave. However, if the pulse width per ILSB is reduced, the signal level of the analog signal obtained by interpolating this PWM wave with a low-pass filter becomes low, and the ratio of the maximum output level to the no-signal level, that is, the There is a drawback that Namino Cleanse deteriorates.

Therefore, in view of the above-mentioned problems, the applicant proposed a PWM
In order to expand the dynamic V/J of the D/A conversion characteristics and improve the linearity, and to enable high-resolution D/A conversion, input digital data is converted into multiple types of PWM.
A D/A converter that adds and synthesizes each PWM wave symmetrically within one conversion cycle (Patent Application 1987-1)
No. 99576) or a D/A converter (patent application No. 58-199577) etc. have been proposed to Zenko.

However, in both cases, the operating frequency of the counter that controls the pulse width has been kept within a practical range, and harmonic distortion caused by frequency modulation distortion and aperture effect has been reduced to improve the linearity of the conversion characteristics. However, D/A with high resolution and excellent linearity used for example in PCM audio etc.
If it is applied to a conversion device, it is difficult to realize because high precision is required for the current source forming the PWM 121, and in particular, it is difficult to provide a D/A conversion device as a monolithic IC.

[Problem that the invention seeks to solve]

As described above, the PWM type D/A conversion has a simple configuration and is suitable for monolithic IC, but the linearity of the conversion characteristic is theoretically inferior to that of the PAM type. In addition, a D/A converter with improved linearity using the PWM method has been proposed, but variations in the multiple current sources used to form the PWM wave affect resolution and linearity, which is required for, for example, PCM audio. It is still not enough to meet the performance requirements.

Since it is still difficult to form this highly accurate current source in a monolithic IC, it is not easy to make a high-performance D/A converter using a PWM method entirely into a monolithic IC.

Therefore, in view of these points, the present invention combines the PAM method and the PW method.
By combining the M method, it is possible to realize a D/A converter with high resolution and excellent linearity even though the high precision required for the current source used in PAM conversion and PWM conversion is significantly relaxed. .

Further, the present invention has high resolution and excellent linearity, can be easily fabricated into a monolithic IC, and enables /A conversion.

[Failure to solve the problem]

In order to achieve the above object, the present invention includes 2N+1 identical current sources and their output switches, an N-bit binary counter, and an N-stage switch circuit whose switching is controlled by an N-bit control signal from the binary counter. It divides the M-bit input digital data into upper N bits and lower (M-N) bits, supplies the upper N-bit data to each stage of the switch circuit, and supplies the lower (M-N) data to each stage of the switch circuit. ) The focus data is converted into a pulse width modulated wave and supplied to the switch circuit.

[Effect]

In the D/A converter according to the present invention, the N-stage switch circuit whose switching is controlled by the N-bit binary counter, the 2N+1 current sources, and their output switches convert the upper N bits of the M-bit input data into PAM.
The lower (MN) waves are converted into PWM waves. Then, the PAM wave and the PWM wave are combined and added together with their time axes aligned and output.

Furthermore, under the control of the switch circuit, all of the two current sources are used equally in forming the PAM wave and the PWM wave within one conversion time.

〔Example〕

An embodiment of the D/A converter according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block circuit diagram showing one embodiment of the present invention. In FIG. 1, a data input terminal 1 is supplied with M-bit serial data obtained by quantizing an analog signal at every sampling period Ts. In this embodiment, 5-bit serial data DSCDo, D+,
D2, Ds, D4] are the above data input terminals 1
shall be supplied to

The serial data Ds is supplied to the data input terminal 1 or the serial/parallel (S/P) converter 2,
This S/P converter 2 uses υparallel data Dp (Do
r D H+ D2 r D3 , D4 ].

Of the parallel data Dp obtained by the S/P converter 2, the lower three pit data Dt, (D2.D, . . .

D4) is supplied to the PWM control section 20, and the upper 2 bit data DH (Dn, D+) is supplied to the PAM control section 30.

The PWM control unit 20 receives a clock pulse φ having a frequency of fcLK, which is supplied from the clock input terminal 11. L.K.
``The 4-bit counter 12 for counting and this counter 12
A 2-bit binary counter 19 is provided which operates using a 1/24 frequency divided output pulse Ps as a clock, and the 2-bit output of this binary counter 19 is supplied to a modulating section 40.

In addition, the PWM control section 20 counts clock pulses φcLK' in the input signal generator 12 to calculate each timing t as shown in FIG. 4-pit counting output data DC (Q,, Q
3. Q2. The first step is to perform match detection for Q, ).
and second coincidence detection circuits 22 and 23'.

The first coincidence detection circuit 22 detects the lower order nL(
The above data D L (D2 + D3) of nL23) bits
+D4) is supplied, and at the same time, a 1-pinotator DS of logic "1" is supplied from the auxiliary data input terminal 24, and this 1-bit data Dst - the above lower nL
4-bit data Dx (DSID,
, Dj, D4) and the count output data D c CQ4 , Q3 + Q2 rQ, /) from the counter 12 to detect a coincidence. The coincidence detection output obtained by the first coincidence detection circuit 22 is supplied to the flip-flop 26 as a reset pulse.

Further, the second coincidence detection circuit 23 converts the one pit data Ds into the lower nL bit data DLCD2, D
Complement data DX of the 4-bit data Dx added to *, D4') is supplied from the complement circuit 25, and this complement data "X" is compared with the count output data Dc to detect a match. The coincidence detection output obtained by the second coincidence detection circuit 23 is supplied to the flip-flop 26 as a signal.

It should be noted that each of the negative number construction circuits 22 and 23 is composed of, for example, four EX-OR gates and one NAND gate.

The flip-flop 26, which is triggered by the minus number outputs from the first and second coincidence detection circuits 22 and 23, operates at each timing t8+j24+.shown in FIG.
At t401 t56 e, a PWM control signal SPwM1f whose pulse width τ changes according to the lower nL bit data DLCD2rD3rD4) is output, and this PWM control signal SPWM is supplied to the modulation section 40. Here, each of the above timings t8+t24+
t40 r t56 is the center of each of the intervals Ta, Tb, Tc, and Td divided into -conversion period Tt--equally spaced intervals.

Further, the output data Bc of the binary counter 19, which operates as the 1/24 frequency divided output pulse Pst'' clock by the 4-bit counter 12, is 2 as shown in FIG.
Among the bits, the lower pit Q1 changes for two cycles in one conversion period T, the upper bit (node Q2 changes for one cycle in one conversion period T), and the lower pit Q1 of the output data BC changes for two cycles in one conversion period T.
is supplied to the modulation section 40 as the switch control signal Sφ1, and the upper bit signal Sφ1 is supplied to the modulation section 40 as the switch control signal Sφ1.

Q2 is sent to the modulation section 40 as a switch control signal Sφ2.
supplied to

Further, the PAM control section 30 is configured to control the PWM control section 20.
The PAM control signals SPAM□ and SPAM2, which are aligned in time with the PWM control signal SPWM output from the PWM control signal SPWM, are used as the upper N pit data (N=2) DHCDo.

D,) and the QPAM control signal SPAMI
.

5PA42 is supplied to the modulation section 40. Here PAM
The control signal SPAM1 is an upper control signal of PAM,
SPAM2 is a lower control signal of PAM.

In this embodiment, the PAM control signal SPAMI I SPAM□ output from the PAM control section 30 and the PWM control signal S P output from the PWM control section 20
WM and switch control signal Sφ2. The modulation unit 40 controlled by Sφ2 has 2 −8 (N, −2) constant current sources a having the same current value.

A current source group 41 consisting of b r C + d + e + f + g r h is provided. Also, this current source group 4
1 to form a PAM wave and a PWM wave.

An output switch circuit 42 consisting of each output switch 56 of b, c, d, e, f, g, and h, a PAM wave and PWM wave full-wave addition synthesis operational amplifier 54, and the output switch circuit 4
A first switch circuit 44 and a second switch circuit 46 are provided. Note that the operational amplifier 54 includes a feedback resistor 53 between the output terminal 48 and the inverting input terminal 55,
It forms an inverting amplifier circuit.

The output switch circuit 42 consists of eight two-contact output switches 56, each of which has a current source a r b + Cr d + er f+ g + of the current source group 41.
connected to h. Then, depending on the signal level supplied to the switch control terminal group 43 of the output switch 56, the connected current source is connected to the ground side or to the operational amplifier 54.
switch to the inverting input terminal 53 side.

ψ1] For example, when the terminal C1 of the switch control terminal group 43 is logic "1", the current source a is connected to the inverting input terminal 5.
When switched to the 5 side and the logic "0", the current source a is switched to the ground side.

A first switch circuit 44 that supplies a control signal to a switch control terminal group 43 in order to control this output switch circuit 42 is composed of eight two-contact switches, four of which are
The input of each switch is the upper PAM control signal SPAMI.
is connected to the input terminal 52 to which C is supplied, and the output signal C of the second switch circuit 46 is connected to the input terminal of the remaining switch.
NI, CN2°CN3. CN4 is supplied.

This first switch circuit 44 has an input terminal 45 connected to the above PW.
The switching is controlled by a switch control signal Sφ1 supplied from the M control section 20. For example, when the switch control signal Sφ1 is logic [J, the input terminal 52 and the terminals C+, Cs, Cs, of the switch control terminal group 43,
When C5 and C7 are conductive and the above Sφ1 is logic "0",
The input terminal 52 and the terminal C2r C4 of the switch control terminal group 43! ca IC8 conducts. Therefore, the upper PAM control signal SPA supplied to the input terminal 52
The M engineer has four current sources a, c, e, and g, and current sources b, d, and f.

Four controls of h are possible in conjunction with the switch control signal Sφ1.

Further, an output signal CNI is sent to the first switch circuit 44.

The second switch circuit 46 that supplies CN2, CN3, and CN4 consists of four two-contact switches, and the inputs of two of the switches receive the lower PAM control signal SP.
It is connected to an input terminal 51 to which AM2 is supplied, and the inputs of the remaining two switches are connected to input terminals 49 and 50 to which the PWM control signal SPWM is supplied. The switching of this second switch circuit 46 is controlled by a switch control signal Sφ2 supplied from the PWM control section 20 to an input terminal 47. For example, when the switch control signal Sφ2 is logic "1", the PAM control signal SPAM2 input to the input terminal 51 is outputted from the output signals CNI, CN.
3 and is supplied to the first switch circuit 44 and input to the input terminal 49.50.
WM is the output signal CN2. The signal becomes CN4 and is supplied to the first switch circuit 44. Therefore, at this time, the PAM control signal SPAM2 controls the two current sources a and e, or the two current sources f0 and the first switch circuit 4.
4, and the PWM control signal S P
WM is the two current sources c and g, or the current source d.
, h can be controlled via the first switch circuit 44.

When the switch control signal Sφ2 is still at logic “0”, the PAM control signal SPA input to the input terminal 51
M2 becomes the output signals CN2, CN4, and the PWM control signal SPWM input to the input terminals 49.50 becomes the output signals CN1. CN3 and the first switch circuit 44
supplied to Therefore, in this case, the PAM control signal S
PAM□ is made possible by the two current sources c and g or the two current sources d and h via the first switch circuit 44, and the pWM control signal S PWM is generated by the current sources a, The two current sources e or the two current sources g and f can be connected via the first switch circuit 44.

Table 1 shows the interval T a + Tb that divides one conversion period T into four equal parts.
, Tc, Td, the PAM control signal SPA
The M-engine SPAM2 and the above PWM control signal S PWM are
This is a table showing which current sources are to be controlled. The sections Ta, Tb, Tc, and Td are formed by the switch control signals Sφ1 and Sφ2, which are the outputs of the binary counter 19, as shown in FIG.

According to this Table 1, - within the conversion period T, the upper PAM
The control signal SPAM1 uses four of each current # twice, and the lower PAM control signal SPAM□ and PWM control signal SPWM uses two of each current source once. That is, two PAM control signals SPAM1+SPAM2
Both the PWM control signal SPWM and the PWM control signal SPWM use all current sources equally through one conversion.

Therefore, the PAM and PWM waves that are formed depend on the average value of all current sources. Here, even if the value of one current source contains an error, the effect will equally affect the formed PAM wave and PWM wave, so the linearity of the output will not deteriorate. . Therefore, even if the current source group 41 does not have high precision, linearity of conversion characteristics by PAM waves and PWM waves can be ensured, and monolithic IC can be easily fabricated.

FIG. 3 shows the current sources a, b, and c used to form PAM waves and PWM waves corresponding to input data.

d + e + f + g + h, and an output waveform P obtained by adding and combining the PAM wave and PWM wave by the operational amplifier 54. UTe is shown.

As mentioned above, the PWM wave has a waveform that is symmetrical about the center of each section in each section Ta, Tb, Tc, and Td, which is divided into four equal parts of one conversion period T't, and is repeatedly formed four times within the conversion period T. be done. Further, the PAM wave is also repeatedly formed four times within one conversion period.

Also, the output waveform P in FIG. Since UT is symmetrical with respect to the center tφ of the -conversion period T, it does not include errors due to frequency modulation distortion, and the conversion characteristics when converted into an analog signal by interpolation with a low-pass filter are eliminated. Errors due to linearity are also reduced.

Furthermore, when attempting to obtain high resolution using the PWM method, the clock frequency that controls the pulse width becomes high, which may exceed the practical range; however, in the present invention, the PWM method is applied to the lower bits of the input data. Therefore, the clock frequency can be lowered. Then, as shown in Fig. 3, the PAM wave corresponding to the upper via) and the PWM wave corresponding to the lower bit are combined and
It is possible to suppress the influence of harmonic distortion on the linearity of conversion characteristics due to changes in the aperture effect due to pulse width fluctuations that occur in the method.

Further, in the embodiment shown in FIG. 1, the input data is a 5-pit D/
Although this is an A conversion device, even when higher resolution is desired, the PAM method is used for the upper two bits and the PWM method is used for the lower bits, and these can be combined as shown in this embodiment. However, if an attempt is made to simply apply the entire PWM method to the remaining lower bits, the lock required to ensure resolution will be too high. In that case, for example, it is effective to further divide the remaining lower order bits, convert them into two different PWM waves, and synthesize them.

〔Effect of the invention〕

As described above, the present invention divides input digital data of M pits into upper N bits and lower (M-N) bits, converts them into upper N bits t-PAM wave, lower M-N bits, )
Convert to PWM waves and convert these into PWM waves.

Since the time axes are combined and combined, harmonic distortion caused by frequency modulation distortion and aperture effect can be reduced, and linearity can be improved. In addition, - PWM wave and PAM wave at conversion time
tj,'l: By using all of the 2N+1 current sources to be formed equally, it is possible to suppress the influence of variations in the current sources on linearity.

Therefore, according to the present invention, a D/A converter with high resolution and excellent linearity can be realized without using a high-precision current source. Furthermore, since high accuracy of the current source is not required, it is easy to form the D/A converter into a monolithic IC.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart illustrating the operation of the PWM control section in the above embodiment 1], and FIG. FIG. 2 is a waveform diagram showing a PAM wave and a PWM wave formed in the section and their combined output signal. Fig. 4 is a waveform diagram showing PAM waves and PWM waves generally used for D/A conversion, and Fig. 5 shows all conversion characteristics of a D/A converter using the above PAM waves and PWM waves. It is a characteristic diagram. 1... Data input terminal, 2... S/P converter, 19
...Binary counter, 20...PWM control section, 30
・・PAM control unit, 40 modulation unit, 41 ・Current source group,
42... Switch circuit, 43... Sinch control terminal group. 44 First switch circuit, 45, 47, 49, 50°5
1.52...input terminal, 46...second switch circuit,
54...Operation amplifier, 56...Output switch time Applicant: Sony Corporation agent Patent attorney
Looking around Koike 1) Sakae Mura - Figure 4 Figure 5 Person 77 Dezuta I Reno 1'5

Claims (1)

[Claims] 2^N^+^Equipped with one identical current source and its output switch, an N-bit binary counter, and an N-stage switch circuit whose switching is controlled by an N-bit control signal from this binary counter, and an M-bit The input digital data of is divided into upper N bits and lower (M-N) bits, and the data of the upper N bits is supplied to each stage of the switch circuit, and the data of the lower (M-N) bits is pulsed. The pulse amplitude modulated wave corresponding to the upper N bit data and the lower (M - A digital device characterized in that the M-bit input digital data is converted into an output of an additive composite wave with a pulse width modulated wave corresponding to the N)-bit data.
Analog converter.