JPH0378321A - D/a conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the increase of the number of clocks by outputting a pair of pulse width modulation(PWM) signals based on pulse width data outputted from a storage circuit and generating an analog signal by means of adding, subtracting and filtering a pair of PWM signals. CONSTITUTION:A first PWM signal output circuit DS11 is constituted of shift registers SR1, SR2, an invertor IV11 and D-type flip flops DF1 and DF2. Outputs from the D-type flip flops DF1 and DF2 are turned into first and second PWM signals. A first analog signal generation circuit AS11 is constituted of low pass filters LP11 and LP12, an operational amplifier AP11 and resistances R11-R14. Then, subtraction and filtering are executed based on the first and second PWM signals having the same pulse width and respectively different logical values based on pulse width data, and the analog signal is generated. Since only one clock is required for the increase of the pulse width when the PWM signal changes by one level, a highly precise D/A conversion circuit can be obtained and the increase in the number of the clocks can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PWM (pulse width modulation) type D/A conversion circuit.

[Prior Art] As a method of converting a digital signal into an analog signal, that is, a D/A conversion method, there is a PWM (pulse width modulation) method. In this method, binary signals having various pulse widths are passed through a low-pass filter to obtain an analog signal.

FIG. 6 shows the P in the above PWM D/A conversion method.
This shows a WM signal sequence. What is important here is that the central axes of the PWM signals adjacent to each other always have a constant period Tf. This is because when the position of the central axis changes, distortion occurs in the analog signal.

FIG. 7 shows the relationship between each PWM signal in the conventional PWM D/A conversion method.

In order to keep the central axis position constant, the pulse width of the PWM signal increases by one clock (Tc) to the left and right each time the level increases by one step. Therefore, two clocks (2Tc) are required for the increase in the level.

[Problem to be Solved] When attempting to realize a highly accurate D/A conversion circuit using the PWM method, it is necessary to reduce the increase in pulse width with respect to the change in the level of the PWM signal. For this purpose, it is necessary to increase the frequency of the reference clock or to reduce the increase in the number of clocks in response to a change in the level. When increasing the frequency of the reference clock, there is an upper limit to the frequency determined by the characteristics of the elements that make up the circuit. Therefore, when it is not possible to increase the frequency of the reference clock, it is preferable to reduce the increase in the number of clocks in response to a change in the level. However, in the conventional D/A conversion method described above, two clocks (2TC) are required for a change in the level.
), which was an obstacle to achieving high accuracy.

An object of the present invention is to reduce the increase in the number of clocks required when a PWM signal changes in level when a high-precision D/A conversion circuit is constructed using the PWM method.

[Means for Solving the Problems] The D/A conversion circuit of the present invention outputs a pair of PWM signals based on pulse width data output from a storage circuit, and performs addition/subtraction and filtering on the pair of PWM signals. It is used to generate analog signals.

[Example] Hereinafter, an example of the present invention will be described based on the accompanying drawings.

Embodiment 1 FIG. 1 is an electric circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1.

First, each component in FIG. 1 will be explained.

BC is a reference clock generation circuit, which is composed of an oscillation circuit and a waveform shaping circuit. This reference clock generation circuit BC outputs a reference clock signal having the same frequency as the oscillation frequency.

CR is a control signal generation circuit that receives a reference clock signal from the reference clock generation circuit BC and sends a control signal to shift registers SRI and SR2, which will be described later.

MR is a memory circuit that stores pulse width data for PWM signals. In this embodiment, the memory circuit MR is composed of a single memory.

SRI and SR2 are shift registers that receive parallel data output from the memory circuit MR, sequentially shift this data, and output the data in series. The shift directions are opposite between shift register SRI and shift register SR2.

IVI1 is an inverter, and shift register SR2
It inverts the output of

DF1 and DF2 are D-type flip-flops that delay the serial output from shift register SRI and the inverted signal of the serial output from shift register SR2 by one clock each.

The above shift register SRI and shift register SR2
, inverter IVI 1, D-type flip-flop DPI
and DF2, the first PWM signal output circuit DS11
is configured, the output from the D-type flip-flop DPI becomes the first PWM signal, and the output from the D-type flip-flop DF2
The output from becomes the second PWM signal.

LPII and LP12 are low-pass filters that convert the first PWM signal and the second PWM signal into analog signals.

APII is an operational amplifier. This operational amplifier AP11
A subtraction circuit is constructed by the resistors R11, R12, R13, and R14.

The above low-pass filters LPII and LP12, operational amplifier APII, resistors R11, R12, R13 and R1
4 constitutes a first analog signal generation circuit ASII.

Next, the operation of this embodiment will be explained using the time chart shown in FIG.

The reference clock generation circuit BC generates a reference clock signal (
a) (Period Tc) is output.

The control signal generating circuit CR receives the reference clock signal (a) and sends a control signal to shift registers SRI and SR2, which will be described later.

The memory circuit MR outputs 6-bit parallel pulse width data. In the example shown in FIG. 2, corresponding to the pulse widths 3Tc, 4Tc and 5Tc of the PWM signal, (
011100), (011110) and (11111
0) is output. This parallel pulse width data is latched in shift registers SRI and SR2, respectively, during the period when shift/latch signal (b) is "O". As a result, shift register SRI
and data terminals D1 to D6 of SR2,
The above data are input sequentially.

The pulse width data latched in the shift registers SRI and SR2 are sequentially shifted at the falling edge of the reference clock signal (a) during the 1° period of the shift/latch signal (b).What is important here is that is that the shift directions of shift register SRI and shift register SR2 are opposite to each other.Shift register SRI
Then, the parallel pulse width data is output in order from the front.

In the example shown in FIG. 2, the pulse width of the PWM signal is 3Tc,
Corresponding to 4Tc and 5Tc, (011100
), (011110) and (111110) are output. On the other hand, the shift register SR2 sequentially outputs the parallel pulse width data from the rear. In the example shown in FIG. 2, the pulse widths of the PWM signal are 3Tc, 4Tc and 5Tc.
Corresponding to -'r c, (OO1110), (0
11110) and (011111) are output. In this way, the signal (C
) and signal (d) are output, respectively.

The signal (C) output from the shift register SRI is D
The first PWM signal (f) is delayed by one reference clock Tc by the type flip-flop DPI. On the other hand, the signal (d) output from the shift register SR2 is inverted by the inverter INII (e), and delayed by one reference clock Tc by the D-type flip-flop DF2.
A WM signal (g) is obtained. The first PWM signal (f) and the second PWM signal (g) are symmetrical with respect to the central axis CEN. Needless to say, the distance between the central axes CEN is a constant value (8Tc).

The first PWM signal (f) and the second PWM signal (g
) is input to low-pass filters LPII and LP12, and an analog output is obtained.

The output signal from the low-pass filter LPII is connected to the resistor R1
1 to the inverting input of the operational amplifier APII,
On the other hand, the output signal from the low-pass filter LP12 is input to the non-inverting input of the operational amplifier APII through the resistor R12. The operational amplifier APII performs subtraction processing on both signals, and a D/A converted analog signal is obtained from its output.

In this embodiment, as is clear from FIG. 2, the pulse width increases by one clock (Tc) when the PWM signal changes in level.

Embodiment 2 FIG. 3 is an electric circuit diagram showing a second embodiment of the present invention, and FIG. 4 is a time chart for explaining the operation of FIG. 3.

First, each component in FIG. 3 will be explained.

The reference clock generation circuit BC, control signal generation circuit CR, memory circuit MR, shift registers SRI and SR2, and D-type flip-flops DPI and DF2 are the same as in the first embodiment. In addition, a second PWM signal output circuit DS12 is configured by the shift register SRI, shift register SR2, and D-type flip-flops DPI and DF2, and the output from the D-type flip-flop DPI becomes a third PWM signal. The output from DF2 becomes the fourth PWM signal.

AS21 is a second analog signal generation circuit, and the third
The PWM signal and the fourth PWM signal are added and filtered to generate an analog signal.

This second analog signal generation circuit AS21 is composed of an operational amplifier AP21, resistors R21, R22, R23, R24 and R25, and a capacitor C21.

Next, the operation of this embodiment will be explained using the time chart shown in FIG.

The operations of the reference clock generation circuit BC, control signal generation circuit CR, memory circuit MR, and shift registers SRI and SR2 are the same as in the first embodiment.

The signal (n) output from the shift register SRI is D
The signal is delayed by one reference clock Tc by the type flip-flop DPI, and a third PWM signal (p) is obtained. On the other hand, the signal (0) output from the shift register SR2 is delayed by one reference clock Tc by the D-type flip-flop DF2, and a fourth PWM signal (q) is obtained.

The third PWM signal (p) and the fourth PWM signal (q
) through resistor R21 and resistor R22, respectively,
It is input to the inverting input of operational amplifier AP21. That is, the operational amplifier AP21 performs addition processing of both signals. Furthermore, since the capacitor 21 is inserted between the input and output of the operational amplifier AP21, low-pass filtering is performed at the same time. In this way, operational amplifier AP2
From the output of 1, a D/A converted analog signal is obtained.

In this embodiment, as in the first embodiment, the pulse width increases by one clock (Tc) when the PWM signal changes in level.

Embodiment 3 FIG. 5 is an electrical circuit diagram showing a third embodiment of the present invention.

First, each component in FIG. 5 will be explained.

The reference clock generation circuit BC1, the control signal generation circuit CR5, the storage circuit MR1, and the second PWM signal output circuit DS31 are similar to those in the second embodiment.

The second analog signal generation circuits AS31 and AS32 also have the same configuration as the second embodiment. However, since the second analog signal generation circuits AS31 and AS32 manually input digital signals having opposite phases to each other, the output analog signals also have opposite phases to each other.

OP is an output circuit, and the second analog signal generation circuit A
Mutually inverted Fll output from S31 and AS32
The analog signal is subtracted and low-pass filtered.

Next, the operation of this embodiment will be explained.

The operations in the reference clock generation circuit BC, control signal generation circuit CR, memory circuit MR, and second PWM signal output circuit DS31 are the same as in the second embodiment. Therefore, the respective outputs of the D-type flip-flops DPI and DF2 “
Q" outputs the third PWM signal (p) and fourth PWM signal (q) shown in FIG. 4, respectively.

The second analog signal generation circuits AS31 and AS32 perform the same operation as the second analog signal generation circuit AS21 in the second embodiment. That is, addition processing and low-pass filtering are performed. However, the second analog signal generation circuit AS31 and AS
32, PWM signals having mutually opposite phases are inputted, so that the output analog signals also have mutually opposite phases.

In the output circuit OP, the second analog signal generation circuit AS3
Subtraction processing and low-pass filtering are performed on analog signals output from AS 1 and AS 32 that are in opposite phases to each other.

In this embodiment, as in the first and second embodiments, the increase in pulse width when the PWM signal changes in level is only one clock (Tc).

Furthermore, in this embodiment, the PWM signals that are in opposite phases are subjected to addition processing and low-pass filtering, and the resulting analog signals that are in opposite phases to each other are subjected to subtraction processing, thereby eliminating the influence of power supply and ground noise. Can be made smaller.

[Effects] In the present invention, the increase in pulse width when the PWM signal changes in level is only one clock, so that high-precision D/A
A conversion circuit can be obtained.

FIG.

MR... Memory circuit DSII... First PWM signal output circuit AS11...
・First analog signal generation circuit DS21...Second P
WM signal output circuit AS21...Second analog signal generation circuit DS31...Second PWM signal output circuit AS3
1...Second analog signal generation circuit AS32...Second analog signal generation circuit or higher

[Brief explanation of drawings]

Claims (2)

[Claims] (1) A memory circuit that stores pulse width data, and a first PWM (pulse width modulation) signal and a second PWM signal that have the same pulse width but different logical values based on the pulse width data. and a first analog signal generation circuit that performs subtraction and filtering based on the first PWM signal and the second PWM signal to generate an analog signal. D/A conversion circuit. (2) A memory circuit that stores pulse width data; and a third PWM (pulse width modulation) signal and a fourth PWM signal having the same pulse width and the same logical value based on the pulse width data. and a second analog signal generation circuit that performs addition and filtering based on the third PWM signal and the fourth PWM signal to generate an analog signal. /A conversion circuit.