JPS6091724A - Digital analog converter - Google Patents

Abstract

PURPOSE:To improve the linearity and to expand the dynamic range by dividing an input data into two; high-order bit and low-order bit, and adding and synthesizing the bits after the high-order bit is converted into a PAM wave and the low-order bit is converted into a PWM wave. CONSTITUTION:A serial data in N-bit quantizing an analog signal is converted into a parallel data by an S/P converter 2. The high-order bit in the parallel data is fed to a shift register 13 via a PAM decoder 15. Each output of the shift register 13 is fed to a switching control circuit 16. The low-order bit of the parallel data is fed to coincidence detection circuits 22, 23 and a complementary circuit 25 and converted into the PWM signal by the circuits. Then the signal is converted into the analog signal by controlling a modulation section 30 with the output of the switching control circuit 16 and the said PWM signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides PCM (Pulse-Code Module)
ation) lz:+-1-1- Digital processing equipment, such as players, is particularly concerned with digital-to-analog conversion devices that convert digital data into pulse amplitude modulation (P).
AM: Pulse-Ampl 1tude Mod
-1ation) wave and path) L-path width modulation (PWM:P
The present invention relates to a system that converts the signal into an analog signal (ulse-width modula-tion) wave and converts it into an analog signal.

[Background technology and its problems]

Conventionally, digital-to-analog (D/A) converters that convert digital signals, such as simple binary codes and binary coded decimal codes, in which each bit has a certain weight, into analog signals have been used to A conversion method in which the above-mentioned digital signal is converted into a PAM wave or PWM wave corresponding to tental information given by weight, and an analog signal is obtained by interpolating the above-mentioned PAM wave or PWMG with a low-pass filter. something is widely known.

A method of converting digital signals into PAM waves (hereinafter referred to as PAM
His name is Fang Ni. )'s D/A converter 4 has a conversion characteristic with good linearity (A) in principle, but it uses a high-shield resistance adder circuit and current that accurately correspond to the weight of each bit of the input digital signal. An adder circuit is required, and if the resolution is to be increased, the circuit scale becomes large and the entire circuit (h) 6 must be made highly accurate. The digital signal is P'
In a D/A converter that converts into WM waves (hereinafter referred to as PwM method), the circuit configuration is simple because the output pulse width can be controlled by a counter according to the input digital signal. In principle, the conversion characteristics are non-linear and include conversion errors, and the operating frequency of the counter needs to be increased depending on the resolution.

In other words, the analog signal converted by the PAM method and the PW
Comparing the analog signal converted using the M method, the first
PA that converted the tental signal using each method as shown in the figure.
The area of the PWM pulse is the same for the M pulse, but the PA does not change the tee with respect to the conversion period T.
The PWM pulse whose data changes with respect to the M pulse is the same as above at full scale (Ii'S). NoE, ・(tl), (tl), (t:
3) is the conversion period (T) TF S , F S , i-F
Because the distance from the center (t) of the analog signal is t, the instantaneous value level of the analog signal becomes lower in the PWM method than in the lJAM method, as shown in Figure 2, and moreover, the conversion characteristics of the method are The nonlinearity changes according to the frequency yc of the analog signal, and the higher the signal frequency, the greater the distortion due to the nonlinearity, and the larger the maximum pulse width of the PWM wave within the conversion period T. I'm sorry that the above distortion has become bigger.

To reduce the conversion distortion in the above PWM force equation, u, PW
By increasing the operating frequency of the counter that controls the pulse width of the M wave, the signal level of the analog signal obtained between the PXVN pass band pass filter that indicates the ILSB of the data becomes low, and the maximum output level There is a drawback that the ratio to the no-signal level, that is, the dynamism 7/watercress decreases.

Furthermore, the /A conversion of the N-bit fractional power is P A
When performing the M method, for example, if a current addition circuit is used, N current sources, which are not weighted with high precision corresponding to each bit, are used.

[Purpose of the invention]

Therefore, in view of the above-mentioned conventional problems, the present invention has been developed by
The object of the present invention is to provide a digital-to-analog conversion device with a novel configuration that enables high-resolution D/A conversion by effectively utilizing the advantages of the AM method and the PWM method.

1. Another object of the present invention is to enable full conversion of D/A conversion using the PWM method, which ensures the full dynamic range without deteriorating the distortion rate of the output analog signal.

Furthermore, another object of the present invention is to
The purpose is to improve the linearity of the conversion characteristics and to avoid obtaining slightly distorted analog signals.

[Summary of the invention]

In order to achieve the above-mentioned object, the digital-to-analog converter according to the present invention divides N bits of input digital data into at least two upper nHN bits, T and lIL bits, and performs amplitude modulation of the upper +11□ bits of data. Convert the data of the lower +1L bit into a pulse width modulated wave, add and synthesize the above Nocil amplitude modulated wave and pulse width modulated wave by combining the time Ra1l, and convert this synthesized pulse within one conversion period. The feature is that it is output multiple times.

〔Example〕

An embodiment of the digital-to-analog converter according to the present invention will be described below in detail in accordance with the drawings. 3. In the embodiment shown in the block circuit of FIG. /Flink Shukan 1 (Period I) 1
The analog signal is quantized to υ and /-N pieces of real data are supplied. In this example, 5hi.

The serial data of 1 is given by the above manual ☆; M child 1,
11.

The signal is supplied to the converter 2, and converted into parallel data by the S/P converter 2.

The parallel data obtained from the above S/P'& converter 2 is
The signal is supplied to the modulation control section 10.

This modulation control section 10 is supplied with a clock f from a clock input terminal 11. Clock pulse with the same wave number as LK (ψ.LK)
It has a 4-bit counter 12 for counting, and a 4-bit first and second shift register 13, 14 each operating as a clock.

Each of the shift registers 13 and 14 has its most significant bit output returned to the serial data input terminal,
The 4-bit data is cyclically shifted using the frequency-divided output pulse (Ps) from the counter 12 as a clock.

The first shift register 13 stores the upper nH (nn=2
) bit data (Dφ), (D+) are passed through the PAM decoder 15 into 4-bit data (dφ), (dl).

(d2), (as) and supplied.

dφ−Nφ〃 d,=Dφ+D.

d2-(Dφ+DI)・D.

d3=Dφ・D.

It is configured by, for example, an OR gate and an AND gate. 4 obtained with this PAM Tecoder 15
Bit data (dφ), (dl), (d2).

(d3) is loaded in parallel into the first shift register 13 at every sampling period Ts, and shifted cyclically in this shift register 13 at every timing of the frequency-divided output pulse Ps as shown in FIG. be done.

The first shift register 13 stores the 4-bit data (dφ), (dl), (d2), (as).
The 4-bit first control data (S
A) is supplied to the switching control circuit 16.

The twisted second shift register 14 is connected to the data input circuit 1
7 to [1, 121, φ, IZI'll] are loaded in parallel every sampling period Ts, and these 4-bit data are loaded in parallel at each timing of the above-mentioned minute output pulse Ps as shown in FIG. The 4-bit second control data (SB) is shifted cyclically as shown in FIG.
is formed and this control data is supplied to the switching control circuit 16.

Further, the switching control circuit 16 receives the 4-bit control data (SA) and (SB) outputted from each of the shift registers 13 and 11 as NOR gates 18 and 1.
It is supplied as the third control data (Sc) via 9.20.21.

Further, the modulation control section 10 applies a clock pulse ψ to the counter 12. By counting □, each timing L is determined as shown in FIG. 4-bit count output data (Qc[:Q+.

Q2. Q3. Q4) )) includes first and second coincidence detection circuits 22 and 23 for detecting coincidence.

The first coincidence detection circuit 22 selects the lower nL (n
b=3) bit data (D2), (D3),
(D4) is supplied, and 1-bit data (Ds) of logic "1" is also supplied from the auxiliary data Kugata terminal 24, and this 1-bit data (Ds) is transferred to the lower nL bit data (D2). ) , (D3) , (D4)
4-bit data (Dx
[Ds, D2, Ds 1D4)) and the above counter 1
Count output data Q c CQ+ from 2.

Q2. Q3. A match is detected by comparing with Qi]. The coincidence detection output obtained by the first coincidence detection circuit 22 is supplied to the flip-flop 26 as a reset pulse.

Further, the second coincidence detection circuit 23 converts the 1-bit data IDs into the lower "L bit data" (D2).

(D3), 4-bit data added to (D4) (D
Complement data (Dx) of x) is supplied from the complement circuit 25, and this complement 3 (Dx) is fully compared with the above-mentioned δj (spread output theta CQC) to detect a match). The coincidence output output from the second coincidence detection circuit 23 is supplied to the flip-flop 26 as a cent pulse.

In addition, each of the above-mentioned minus number configuration circuits 22 and 23 has, for example, an EX/OR gate of 11 units and a N A N circuit of 1 unit.
l) Consists of Kate.

The flip-flop 26 triggered by the negative outputs from the first and second coincidence detection circuits 22 and 23 operates at each timing (t8) - (t
2. ), (t4o), (tso) and the above lower order]]L bit data (D3), (D4)
, (D5) P whose pulse width (τ) changes according to
WM! Outputs till H signal (SPWM). Here, each of the above timings (t8)'(t24), (
t4o), (t5e) are −conversion 1. 'jj period (T) is divided into equal intervals (TIl), (Tb), (
Tc), the center of (T, i) ((becomes.

In this embodiment, the modulation pill side +i[1o controls the operation fl+ of the modulation unit 30 configured as described above.
It has 2nH=4 constant current sources 31, 32, 33, 34, and is configured as follows.

Each constant current source 31.32, 33.34 has one changeover switch 35.36.3γ with three contacts.

38'6 possible 11 contacts (s+), (S2),
(S3) and (s,+) are connected. And each of the above-mentioned changeover switches 35°36.37.38U, each first fixed contact (AI), (A2).

(A3), (A4) are connected to the inverting input terminal of the operational amplifier 40, and each second fixed contact (B+) including 1/9
, (B2).

(B, ), (B+) are connected to the above-mentioned inverting input pair, one child through the PWM switch 39, and each third
Fixed contacts (c,) , (C2) , (C3) ,
(C4) or grounded t'.

As mentioned above, the operational amplifier 4 (01) has its non-inverting input terminal connected to the ground, and its output terminal 41 is connected to the inverting input terminal via the feedback resistor 42.

The PWM switch 39 is the PWM output from the flip-flop 26 of the modulation control m+ section io.
ffi control signal (SPWM)
111 is now available.

1, the above four changeover switches 35, 36, 37° 38
is controlled in the following manner by the switching control signal (Ssw) output from the switching control circuit 16 of the modulation 1h control section 10 described above.

When the most significant bit output ', Q+3) of the first shift register 13 of the modulation control section 10 is logic "1", the movable contact of the first changeover switch 35 is activated by the switching control signal Ssw. (S+) is connected to the second fixed contact (AI), and the second
When the most significant bit output (Q23) of No. 4 is logic (-1), the movable contact (Sl) is the second fixed contact (j3+)
Furthermore, each of the most significant bit outputs (Q1
0, Q23) and both logic [-〇''), the driving contact (Sl) of I/C1 is connected to the third fixed contact +-mu\4. That's right, number 2. Third. Fourth changeover switch 36
．． Similarly to the first selector switch 35, the switches 37 and 38 can be switched according to the logical values of the outputs of the shift registers 13 and 14.

The four changeover switches 35, 36, 37, and 38 are used to select the first! output from the first shift register 13. The sections (Ta) and (Tb) in the time chart shown in FIG. 4 above are determined by the ti control data A).

Four constant current sources 31, 32 for each (T,), (Td)
, 33°34 to the above top 11+1 binotator (Dφ
), (D, ) are sequentially selected to form a pAM wave (PAMo) as shown in FIG. 5, and this PAM wave (PA11xIo) is supplied to the operational amplifier 40.

35.36.37゜3
8i! , the second flil+control data output from the second /ftre/star 14 causes the above-mentioned one constant current source 31.32, 33.34 to be adjusted to each of the above-mentioned sections (T
-), (Tb) = (Tc), (Td) 4u
l1lf4 then select switch 3 for manual PWM
Connect to 9. The PWlvI switch 39 performs the PWM control (PWMe) by performing all switching operations based on the L month.

(I)WMO) to form this PWM wave (PWiVI
o) is supplied to the operational amplifier 40.

The operational amplifier 40 includes each of the switches 35 described above.
．． 36.37, 38.39, the PAM wave (p
AMO) and PWM wave (PWM, ) are added and synthesized to generate the sixth
Outputs a composite pulse (POUT) as shown in the figure.

That is, in the embodiment configured as described above, the lower +11 . Pino Tochi ~ Riga, -
Each interval (T, ) is obtained by dividing the conversion period (T) into equal intervals.

The pulse width (τ0) is symmetrically centered around the center timing of (Tb), (Tc), and (Td).
A PWIVI wave (
PWj\qo). The above PWM wave (PWIV
]o) has the same pulse width (τ) that is symmetrical within the conversion period (T) and has the same pulse width (τ.) within the conversion period (T) and is sequential θζ
Since the signal consists of four PWM pulses that are output to the same number of pulses, when the signal is interpolated by a low-pass filter and converted into an analog signal, the signal level can be increased by the number of pulses without increasing the distortion factor.

[Binoto data is the above-mentioned PWM wave (PWMo) and the above-mentioned heat interval (Ta), (Tb), (1
'c) It is converted into a PAM wave (PAMo) consisting of four PAM pulses each having a pulse width of ('L+). The above PAM wave (p AMo) has a −conversion period (T
), it is possible to reduce conversion distortion of the PAM wave due to the so-called aperture effect. In addition, upper 3 members P.A.M.
Each pulse/pulse interval of a(PAMo) is arbitrary, but the shadow of the above aperture effect @! In order to reduce (, it is better to make the interval smaller.

Furthermore, in this embodiment, the PAM wave (PAMo) and the PWM wave (PWMo) are converted to each constant current source 31, 32, 33, 34 of the modulator 30 by j1h within one conversion period (T).
Next, since it is formed by switching and selecting, each constant current value (it) of each constant current source 31, 32, 33, 34,
The overall wave height value can be shown by the average cylinder of (I2), (I3), and (I4). Therefore, PAM waves (PAMo) and pWM waves (PWM,
It is possible to ensure the linearity of the conversion characteristics due to this, making it easy to implement a monolink IC.

The above PAM wave (P A Mo ) and PWM wave (PWMo
The synthesized pulse (Poul・) obtained by adding and synthesizing
Errors due to non-linearity of the conversion characteristics when the signal is interpolated by a low-pass filter and converted into an analog signal are also reduced as shown in FIG.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, in the digital-to-analog converter according to the present invention, N-bit input digital data is divided into at least two parts, the upper 1111 bits and the lower ILL bits, and each take is divided into one conversion period. Multiple symmetrical PAM waves and PW with equal pulse width within
Since it is converted to M wave and added and synthesized by aligning the time axis,'
D/A conversion with excellent linearity and a wide dynamic range can be performed without including errors caused by IFM components.

Therefore, according to the present invention, the intended purpose can be fully achieved.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing PAM waves and PWM waves generally used for D/A conversion, and Fig. 2 shows a comparison of each conversion characteristic of D/A conversion using the above-mentioned PAM waves and PWM waves. It is a characteristic line diagram. Figure 3 is a waveform diagram of the PAM wave obtained by converting the take of the upper nll bits in the above embodiment, and Figure 6 is the summation of each PWM wave in the above embodiment. FIG. 7 is a waveform diagram showing an example of a PWM wave output obtained by synthesis, and a characteristic line diagram showing D/A conversion characteristics in the above embodiment. 10 Modulation 11i11 Hj section 12... Counter 13.14... Shift register 15... PAM decoder 16 - Switching control circuit 22.23 - Number construction circuit 25... Complement circuit 26... Flip-flop 30 ... Modulation section 31.32.33.34 ... Constant current source 35.36.3γ, 38.39 ... Switch 40 ...
・Operational amplifier patent applicant Sony Corporation agent Patent attorney Brother Koike 1) Toshiei - Procedural amendment (voluntary) August 711, 1981 Commissioner of the Japan Patent Office Manabu Shiga 1, Indication of the case 1988 Patent Application No. 199197 @2, Relationship with the title of the invention A'I Special a'"Applicant's name: 6-7-35, Kitahana, Tokyo Parts Co., Ltd. (
218) Sony Corporation (Name) Representative: Norio Ohga4, Agent: 105 Address: 6-4 Toranomon 2-chome, Minato-ku, Tokyo Vol. 6; "Explanation" column, drawing 7, content of amendment (7-1,) From page 3, line 15 of the specification to page 8 of the same page
The statement "In order to leave, including..." that spans several lines is corrected as follows. Frequency modulation (F' M : Freq
An error is generated due to ``uencyModulation''. In addition, as shown in Figure 2, the instantaneous value level of each analog signal converted by each method is
The M method is higher, and the conversion characteristics by the PWM method have nonlinearity. ” (7-2) The statement “with a higher height,” on the 7th line of page 4 of the specification is corrected to “with a higher value.” (7-3) On the 10th page of the specification: Description 1 on line 10
Correct "M88 example" to "IMsB side". (7-4) The statement ``1 matching output output'' on page 11, line 4 of the specification is corrected to ``1-several configuration output output''. (7-5) The 11 statements ranging from line 7 on page 11 to line 8 of the same page of the specification ``NAND K-1'' are replaced by 14 EX-01 ( , Kate and 1 N
"OLL K-I-de," he corrected. (7-6) Statement on page 11, line 13 of the specification [
Above lower 11L......, (to Dsl) is changed to "
Above lower 11L hit 1, take (D 2), (D a
”), (D 4')”. (7-7) Statement on page 13, line 9 of the specification [Q
,, Correct J to "Qlφ". (7-8) From page 13, line 11 of the specification to page 8 of the same page
The description over the lines 1 and 2...... Output (
"Q2B)" is corrected to "Is it also the most significant hit output rQ2φ) of the second shift register 14?" (7-9) Statement on page 13, line 15 of the specification [
Correct Q+-, Q2j to IQ, φ, Q2φ]. (7-10) From line 4 of page 16 of the specification to line 8 of the same page
Description spanning lines 1 The above FAM wave (PAMo) is...
··be able to. Delete J. (7-11) Figure 2 of the drawings will be corrected as shown in the attached sheet. Go to Figure 2

Claims (1)

[Claims] The entire N-bit input digital data is divided into at least two parts, the upper nN bits and the lower 11L bits, and the upper II N
Convert all bit data into a pulse amplitude modulated wave of 114 waves, convert all of the lower nL bit data into a pulse width modulated wave,
A digital-to-analog conversion device characterized in that the pulse amplitude modulated wave and the pulse width modulated wave are added and synthesized with their time axes aligned, and the synthesized signal is output multiple times within one conversion cycle.