JPS6086848A - Substrate for mounting of semiconductor element - Google Patents
Substrate for mounting of semiconductor elementInfo
- Publication number
- JPS6086848A JPS6086848A JP58194891A JP19489183A JPS6086848A JP S6086848 A JPS6086848 A JP S6086848A JP 58194891 A JP58194891 A JP 58194891A JP 19489183 A JP19489183 A JP 19489183A JP S6086848 A JPS6086848 A JP S6086848A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- fitting
- mounting
- elements
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、複数個の半導体素子を一体の半導体装置とし
て組み込むための半導体素子搭載用基板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor element mounting substrate for incorporating a plurality of semiconductor elements into an integrated semiconductor device.
従来、このような、複数個の半導体素子を一体の半導体
装置とするには、素子を並列してマウントする方式、ｔ
ｆｃは半導体素子を搭載した基板を重ね合せる方式、あ
るいは同一の基板上にいくつもの素子を組込む方式など
がとられて％／−ｈ７ｔ ６しかしながら、これら従来
の方式は、実装面積が増大するとか、重ね合せの特別の
部品が入用となるなどの欠点があった。Conventionally, in order to integrate a plurality of semiconductor elements into an integrated semiconductor device, there has been a method of mounting the elements in parallel.
For fc, a method is used in which boards on which semiconductor elements are mounted are stacked, or a number of elements are incorporated on the same board. There were drawbacks such as the need for special parts for overlapping.
本発明の目的は、これら従来の欠点を解決した半導体素
子搭載用基板を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate for mounting a semiconductor element that solves these conventional drawbacks.
本発明の半導体素子搭載用基板は、半導体素子が搭載さ
れる搭載面を有する絶縁体の基板の複数個を含むもので
、これら複数個の基板のそれぞれには嵌合により一体に
組立てるための四部または凸部が設けられている構成を
有する。The substrate for mounting a semiconductor element of the present invention includes a plurality of insulating substrates each having a mounting surface on which a semiconductor element is mounted, and each of the plurality of substrates has four parts that are assembled together by fitting. Or, it has a configuration in which a convex portion is provided.
本発明の半導体素子搭載用基板では、基板自体が嵌合部
を有し、半導体素子を搭載した状態で、複数個を嵌合組
合すことにより、簡潔に一体にまとまった半導体装置を
容易に得ることができる。In the semiconductor device mounting substrate of the present invention, the substrate itself has a fitting portion, and by fitting and combining a plurality of semiconductor devices with the semiconductor device mounted thereon, it is possible to easily obtain a simple integrated semiconductor device. be able to.
つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.
第１図は本発明の一実施例の斜視図を示し、同図（ａ）
は２個で一体化するための一方の基板に半導体素子を搭
載した状態の斜視図である。第１図（ａ）において、基
板本体１に埋込まれ７’Ｃ３本のリードピン２，２．２
が、基板本体の長さ方向の一つの端面から外部に引き出
され、また、本体１の素子搭載面１ａには、搭載用凹み
が設けられ、この凹みに半導体素子３が搭載され、素子
搭載部の周囲に突出させたリードピン２，２．２の他端
と素子３のボンディングパッドとの間は金属細線４でも
ってワイヤボンディングされ４いる。さらに、搭載面１
ａの反対側の面には嵌合用の凹部５が設けられている。FIG. 1 shows a perspective view of an embodiment of the present invention, and FIG.
FIG. 2 is a perspective view of a state in which a semiconductor element is mounted on one substrate for integrating two semiconductor elements. In FIG. 1(a), three lead pins 2, 2.2 of 7'C are embedded in the board body 1.
is pulled out from one end surface in the length direction of the substrate body, and a mounting recess is provided in the element mounting surface 1a of the main body 1, and the semiconductor element 3 is mounted in this recess, and the element mounting portion The other ends of the lead pins 2, 2.2 protruding around the periphery of the element 3 and the bonding pads of the element 3 are wire-bonded with a thin metal wire 4. Furthermore, mounting surface 1
A recess 5 for fitting is provided on the surface opposite to a.
このような、半導体素子を搭載した基板構体１１は、第
１図（ｂ）に示すように、嵌合凹部５に合致する凸部６
を有するだけで、その他は同様構造の基板構体１２と嵌
会組合せにより一体化されている。As shown in FIG. 1(b), such a substrate structure 11 on which a semiconductor element is mounted has a protrusion 6 that matches the fitting recess 5.
, and is otherwise integrated with the substrate structure 12 having the same structure by fitting.
第２図は本発明の他の実施例の斜視図である。FIG. 2 is a perspective view of another embodiment of the invention.
同図（ａ）は４個で一体に組合せられる基板の一つを示
す斜視図であり、基板本体１０には第１図と同様のリー
ドピン２，２．２が埋込まれており、素子搭載面１０ａ
には素子搭載用の凹み３ａを有する。さらに、本体１０
の幅方向の両側面鉱、４個の基板を組合せるために搭載
面１０ａに対し内側に入るテーパ付けがされ、かつ、こ
のテーパの一つには嵌合用の凹部１５、反対側のテーパ
には嵌合用凸部１６が設けられている。そして、このよ
うな搭載基板の４個は第２図（ｂ）のように、側面の嵌
合凸部１６を隣り合う基板の嵌合凹部１５に嵌合させ、
順繰りにリング状に組合せて一体化されるＯ
第３図は、第１図（ｂ）に示す組合せ構体に対し、例え
ば樹脂６で密封して、複数の半導体素子が簡潔な形で一
体にまと゛まった半導体装置としたものである。 −FIG. 1(a) is a perspective view showing one of the four boards assembled into one. Lead pins 2, 2.2 similar to those in FIG. 1 are embedded in the board body 10, and elements are mounted. Surface 10a
It has a recess 3a for mounting an element. Furthermore, the main body 10
Both sides in the width direction of the board are tapered inward to the mounting surface 10a in order to combine the four boards, and one of the tapers has a recess 15 for fitting, and the opposite taper has a recess 15 for fitting. A fitting convex portion 16 is provided. Then, as shown in FIG. 2(b), four of these mounting boards fit the fitting protrusions 16 on the side surfaces into the fitting recesses 15 of the adjacent boards, and
In contrast to the combination structure shown in FIG. 1(b), FIG. 3 shows a structure in which a plurality of semiconductor elements are integrated in a simple manner by sealing with resin 6, for example. This is a compact semiconductor device. −
第１図（ａ）は本発明の一実施例に係る２個組合せのう
ちの一個の素子搭載基板に半導体素子を搭載した状態を
示す斜視図、同図（ｂ）は、同図（ａ）の基板構体と相
手の基板構体を組合せた状態を示す斜視図、第２図（ａ
）ＪＩ′ｉ、本発明の他の実施例に係る４個組合せのう
ちの単位の一個の素子搭載基板を示す斜視図、同図（ｂ
）は同図（ａ）の基板の４個を組合せた状態を示す斜視
図、第３図は第１図（ｂ）の基板構体を組合せ後に封止
した状態を示す斜視図である。
１．１０・・・・・・基板本体、２・・・・・・リード
ピン、３・・・・・・半導体素子、４・・・・・・金属
細線、５．１５・・・・・・嵌合凹部、６．１６・・・
・・・嵌合凸部、１１，１２・・・・・・基板構体０
第２図
第３図FIG. 1(a) is a perspective view showing a state in which a semiconductor element is mounted on one element mounting board of a two-piece combination according to an embodiment of the present invention, and FIG. FIG. 2 (a) is a perspective view showing the combination of the board structure of
) JI'i, a perspective view showing one element mounting board of a unit of four combinations according to another embodiment of the present invention, the same figure (b
) is a perspective view showing a state in which four of the substrates shown in FIG. 1(a) are combined, and FIG. 3 is a perspective view showing a state in which the board structures shown in FIG. 1(b) are assembled and sealed. 1.10... Board body, 2... Lead pin, 3... Semiconductor element, 4... Thin metal wire, 5.15... Fitting recess, 6.16...
...Fitting convex portion, 11, 12... Board structure 0 Fig. 2 Fig. 3
Claims (1)
の基板から構成され、これら複数個の基板は嵌合により
一体に組立てるための凹部または凸部がそれぞれに設け
られていることを特徴とする半導体素子搭載用基板。It is composed of a plurality of insulating substrates each having a mounting surface on which a semiconductor element is mounted, and each of these plurality of substrates is provided with a concave portion or a convex portion for assembling them together by fitting. A substrate for mounting semiconductor elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58194891A JPS6086848A (en) | 1983-10-18 | 1983-10-18 | Substrate for mounting of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58194891A JPS6086848A (en) | 1983-10-18 | 1983-10-18 | Substrate for mounting of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6086848A true JPS6086848A (en) | 1985-05-16 |
Family
ID=16332044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58194891A Pending JPS6086848A (en) | 1983-10-18 | 1983-10-18 | Substrate for mounting of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6086848A (en) |
-
1983
- 1983-10-18 JP JP58194891A patent/JPS6086848A/en active Pending
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