JPS6085626A - Decoder - Google Patents

Abstract

PURPOSE:To allow the decoder to cope with the case when reception data is inputted consecutively by connecting an output of a syndrome register to a location calculating circuit so as to have a correction execution circuit thereby eliminating the need for shifting a syndrome register for the purpose of calculation of location after the input of the reception data. CONSTITUTION:The inputted reception data 1 is stored in a buffer resister 4 and a syndrome is calculated by a syndrome register 2 at the same time. When the input of reception data is finished, the syndrome is inputted to a location calculation circuit 12 from the syndrome register 2 and binary numbers 0-56 representing error position are outputted from the location calculation circuit 12 instantly. Then a location is inputted to a correction execution circuit 13, but when a buffer register 4 is shifted immediately after the end of input of the reception data 1, a correction pulse is generated from a correction execution circuit 13 in the timing when the erroneous data is outputted from the buffer register 4, an output of the buffer register 4 is inverted by an exclusive OR gate 5 and correction is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding device, and particularly to a decoding device for performing error correction using a binary code of code length n (n is a positive integer).

[Description of prior art] Code length n, number of information points, code open circuit ff1td(n, k.

In explaining a conventional circuit of a decoding device that decodes an error correction code (d is a positive integer), as an example, code length r1-63,
FIG. 1 shows a case where the information score is -57. In the figure,
1 is the received data consisting of a serial binary code and 63-bit error correction codes are arranged in sequence, 2 is the syndrome register that calculates the syndrome based on the received data 1, and 3 is the input bit number 6 with an input cover turn of '100000''. 4 is a buffer register consisting of a 57-stage serial input-serial output shift register, and 5 is an exclusive OR that outputs the exclusive OR of two people. 6 is decoded data which is the decoded output, and 7 is a shift register composed of flip-flops.

Also, to help explain, in Figure 2, n = 63°k =
57 shows an encoder for the BCH code of 57. In the figure, 8 is information data that does not include an error correction code, 9, 10 is a switch, and 11 is transmission data with an error correction code.

Generally, the code length n, the number of information points, and the inter-code distance d (n
, k, d) The linear code is generated as follows.

■K bits of information in order (lllo, 1114...
....

IIK-1).

(2) This information is expressed as a polynomial of order +11(X). That is, Ill (X)'-m. +rn, x+l112x2+J
-'-・+m
(X) Divide t'X"-111(X) and find the remainder R(X). That is, X"=・m (x)-Q(n)・g (X>+R(X
) (mad, 2) ... (2) ■ ,n-H,'' If the sum of (x) and R(x) is the code polynomial E(x), then F (, x) -x''-' −m (x) +R(x
) (mad.

2) =Q (X) ・Q (X) <mod, '2>
...〈3).

It is clear from the above description that the code polynomial F(x) generated in this way is divisible by the generator polynomial g (x). This F (X ) is defined as the code word (aO
+al *a2 *...+"n-1) and sent to the transmission path.

On the other hand, the above code is decoded as follows.

That is, ■ Calculate the syndrome of received data.

■ Count the binary number (error location) that indicates the error location.

■ Perform error correction.

Let me explain more specifically. Now, the received data (b o
, bl +b2 , ++ +bT1-1 >, the syndrome is obtained as the remainder when the received data is divided by the generator polynomial g (x). In other words, the remainder F(α) is
F(α)-b. +b, α+b2α2+・・・・・・+b
,, α0゛1 +1-eo+e, α+e2α2+...+en-
1α”1 ...<4) Here, e-(e O1e+ le2
1..., enJ> indicates an error pattern. If a of the transmission data (aO+al +...+an-1). -1
Assuming that the received sequence is caused by an error in the third bit counting from This is the third number of error locations.

Next, calculate j from the number of error locations αn-j.

Generally, the syndrome sieve circuit is a division circuit by a<X>, but shifting the contents of this division circuit once means that the contents of the division circuit can be shifted by the remainder modulo 0(X) stored in the shift register. It is equivalent to multiplying by α. When the received data has been input, αn- is stored in the syndrome register.
Since j is stored, αn-j·αj-1 can be obtained by shifting it once. That is, at the same time as shifting the syndrome, the received data stored in the buffer register is shifted and output, and when the pattern of 1 = (100...O) is displayed in the syndrome register, the output of the buffer register is By reversing it, the error is corrected.

In the following, to simplify the explanation, the (63.57.3) BCH code derived from g(x)=x'+x+1 (6) will be explained as an example.

FIG. 2 shows a (63,57,3) BCH code encoder, in which all shift registers 7 are reset to O at first. Also, the switch 10 is pushed down, and the switch 9
is closed. Information data → m = ('OrI111+”' *J G ) is N m
A of the transmission data 11 is sequentially fetched into the shift register 7 in the order of L 6 r ” S S +...+"O, and the remainder is calculated.

2 +aG + 1...ta6 is sent to the transmission path. When you finish inputting the information data, press switch 1.
0 is pushed upward, the switch 9 is opened, and the remainder remaining in the shift register 7 is transferred to the transmission line am +8 of the transmission sequence.
4 +8m +a2 +al +aO.

A decoding apparatus as shown in FIG. 1 has conventionally been used to decode the codes as described above. Received data 1 input to the decoding device in FIG. 1 is stored in a buffer register 4, and at the same time, a syndrome is calculated by a syndrome register 2.

When the input of the received data is completed, the buffer register 4 is shifted, and at the same time as the data is read out, the syndrome register 2 is shifted to "100000".
The output hit at the time when the 1o o o o o'' pattern is detected by the pattern detection circuit 3 is inverted by the exclusive OR gate 5 and corrected.

Since the conventional decoding system was configured and operated as described above, it was necessary to shift the syndrome register even after inputting the received data, and it was necessary to have idle time after inputting the received data. .

Therefore, if the system is to cope with the case where received data is input continuously, there is a drawback that a plurality of syndrome registers must be provided.

[Summary of the Invention] Therefore, the present invention has been made in order to eliminate the drawbacks of the conventional device as described above.

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus that can perform decoding processing even when received data is continuously input by providing a separate location calculation circuit, without calculating the location using a syndrome register.

[Embodiment of the invention] ・Hereinafter, an embodiment of the present invention will be described using the generating polynomial 〇(X)−X
The case of the (63,57,3) GCH code of 6+X+l will be explained with reference to the drawings as an example.

FIG. 3 shows an embodiment of the present invention (63°57.
3) It is a block diagram showing a DCH code decoding device. In FIG. 3, 12 is the syndrome (S5゜S4 +S8 +S2 +
Sl *SO), the error position is set to 0-k (in this case, k
=57> as a binary number (Lo.

A location calculation circuit 13 outputs the outputs (Lo, LI, L2, L-, L4, LS) of the location calculation circuit to (Do IDI, D2, Ds, D<, Ds)
A correction execution circuit outputs a correction signal at a timing designated by the input binary number, and 14 is a correction signal output from the correction execution circuit.

An embodiment of the present invention configured as described above corrects errors as follows. In FIG. 3, input received data 1 is stored in a buffer register 4, and at the same time, a syndrome is calculated by a syndrome register 2. When the input of the received data is completed, the syndrome is transferred from the syndrome register 2 to the location calculation circuit 1.
2, and the location calculation circuit 12 immediately outputs a binary number from 0 to 56 indicating the error position. This location calculation circuit, for example, uses a syndrome as an address and a location as data to write R.
Use OM. If the information data ""'("66J$5 + +1io) with 6 at the beginning, ■
Assuming that the location where an error occurs is j+1, the ROM address chart will be as shown in the attached table. If the code has a short code length n, a logic circuit can be used instead of a ROM. The same effect can be obtained in this case as well.

Next, the location is changed to the correction execution circuit 1 and 3, but since this is done instantaneously, if the buffer register 4 is shifted immediately after inputting the received data 1, the erroneous data can be A correction pulse is generated from the correction execution circuit 13 at the timing when is output from the buffer 7 register 4, and the output of the buffer register 4 is inverted by the exclusive OR gate 5 to perform correction.

FIG. 4 shows an example in which the correction execution circuit 13 is configured using a decoder and a shift register.

In FIG. 4, 15 is the output of the location calculation circuit (
Input (Lo, L+, 12', L-, L-, Ls) (Do, DI, D2.0-, D4, Ds
) and E depending on the input binary number. A decoder 16 which sets one of the outputs of -Ej6 to "H''' is an error register which receives the output of the decoder, performs parallel/serial conversion, and is composed of a shift register having the same number of stages as the buffer register 4.

In Fig. 4, now information data m = (1”56*11
114 r..., rno), the location is j+1, and when a binary number indicating j+1 is input, the decoder 15 sets only Ej to "H". The error register 16 is inputted in parallel, shifted in series at the same timing as the buffer register 4 is shifted, and the correction pulse 14 is output at the timing when the erroneous data is output from the buffer register 4. .

Furthermore, FIG. 5 is a block diagram showing an example in which the correction execution circuit 13 is configured using a counter with a preset. In the figure, 17 is a preset counter whose preset input is the output of the location calculation circuit, and 18 is a pattern detection circuit "i1-1001" which outputs a pulse when the output of the preset counter reaches "111001". 19 is the preset instruction for the counter with preset, and the root number is B. 20 is "11100".
1''/l->A flip-flop is set by the output of the detection circuit, reset by the load signal, and outputs a reset signal for the preset counter.

If the correction execution circuit 13 is configured using a counter with a preset as shown in FIG. 5, a large number of elements will be required even in the case of a long code as in the case of the configuration shown in FIG. It has the advantage of not being

Now, as in the case of FIG. 4, consider the case where location j+1 is input. The preset counter 17 is preset by the load signal 19 and j+1
The count is increased in synchronization with the shift of buffer 7 register 4.

On the other hand, the 111001'' pattern detection circuit 18 outputs a pulse when the output of the preset counter 17 becomes '111001'', that is, at the timing of 57, and the flip-flop 20 is set by this pulse. Therefore, the preset counter 17 will be reset until the next location occurs.

On the other hand, the output of the 'i i i ooi' pattern detection circuit 18 is the shift 1 to start completion 57-j of the buffer register 4.
The timing when the th data is output, i.e. mj
“1” occurs because it occurs at the timing when the data of “1” is output.
11001''' The output of the pattern detection circuit 18 is a correction pulse 14.

[Effects of the Invention] As described above, according to the present invention, the output of the syndrome register is connected to the location calculation circuit and is configured to have a correction execution circuit. Furthermore, there is no need to shift the syndrome register, and the decoding device can handle cases where received data is input continuously.

Further, even in the case of a long code, the decoding device can be constructed with a simple circuit.

(YZ Shimoaki et al.) Separate table

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional decoding device. FIG. 2 is a diagram showing a decoder for a (63,57,3) BCH code. FIG. 3 shows an embodiment of the present invention (63,57
, 3) is a circuit block diagram showing a decoding device for BCH code. FIG. 4 is a block diagram showing an example in which the correction execution circuit in the embodiment shown in FIG. 3 is configured using a decoder and an error register. FIG. 5 is a block diagram showing an example in which the correction execution circuit in the embodiment shown in FIG. 3 is configured using a counter with a preset. In the figure, 1 is received data, 2 is a syndrome register, 3 is a "100000" pattern detection circuit, 4 is a buffer register, 5 is an exclusive OR gate, 6 is decoded data, 7 is a shift register, 8 is information data, 9.10
11 is a switch, 11 is transmission data, 12 is a location calculation circuit, 13 is a correction execution circuit, 14 is a correction pulse, 15
16 is a decoder, 16 is an error register, 17 is a counter with a preset, 18 is a '111001' pattern detection circuit, 19 is a load signal, and 20 is a flip 70 tube. In the figures, the same numbers refer to the same or equivalent elements or The device is shown. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Procedural amendment 9 issued in 1925/2017/To the Commissioner of the Japan Patent Office 1. Indication of the case: Japanese Patent Application No. 58-195546. Agent 5, Detailed explanation column 6 of the invention of the subject of amendment Mei ms, Contents of amendment (1) Mei S * Page 3, line 20 to page 4, line 2 [
``Received data in which 63-bit error correction codes are sequentially arranged'' is corrected to ``63-bit received data including error correction codes.'' (2) Mei IB, page 10, lines 9-10 r
G Cl-1 Futan” and rDcI-1 on line 13 of the same page.
"code" are respectively corrected to "rBcH code". (3) Akima page 111, line 18 (7) rm ni is wrong, but J is corrected to ``mJ is wrong.'' (4) Correct "buffer 7 register 4 shifted" in line 7 of page 13 of the book to "buffer register 4 shifted". that's all

Claims (5)

[Claims] (1) Sign @ imperial length n, number of information points, and inter-symbol distance d(n,
, d is a positive integer) is a decoding device for decoding an error correction code, which includes a syndrome register consisting of (n − k ) flip-flops and an exclusive OR circuit, and a syndrome register having the number of input data pits. (n − k ), and the number of output data focuses is m
(p''-'<k≦2'': m is a positive integer) and outputs the error position as a binary number based on the syndrome decoding table; and a k-bit serial input-serial output shift register. and a correction execution circuit which outputs a pulse for executing error correction based on a binary number indicating the error position of the input data number mT'' where the number of input data is m, and an output terminal of the syndrome register. and an input terminal of the location calculation circuit, and an output terminal of the location calculation circuit and an input terminal of the correction circuit are respectively connected to perform error correction. Device. (2) The location calculation circuit has the number of input data pits (n − k ) and the number of output data pits m
(2''-'<k≦2m), and is constructed using a read-only memory (ROM>) in which a binary number indicating an error position is written in advance in a decoding table based on the syndrome. The decoding device according to scope 1. (3) The decoding device according to claim 1, wherein the location calculation circuit is constituted by a logic circuit. (4) The correction execution circuit has a decoder in which the number of input bits is 0, the number of output bits is k, and only the output of the output terminal specified by the input is set to "gt 1 (high level)"; 4. The decoding device according to claim 2, wherein the decoding device is constituted by an error pattern register consisting of a k-stage parallel/serial conversion shift register. (5) The correction execution circuit has an m-bit preset binary counter, a coincidence circuit that outputs an output pulse when a value obtained by dividing k by i in binary is input, and a set input and a reset input. The decoding device according to claim 2 or 3, characterized in that it is constituted by a flip 70 tab.