JPS6085545A - Method for formation of bump electrode for semiconductor element - Google Patents

Method for formation of bump electrode for semiconductor element

Info

Publication number
JPS6085545A
JPS6085545A JP58194626A JP19462683A JPS6085545A JP S6085545 A JPS6085545 A JP S6085545A JP 58194626 A JP58194626 A JP 58194626A JP 19462683 A JP19462683 A JP 19462683A JP S6085545 A JPS6085545 A JP S6085545A
Authority
JP
Japan
Prior art keywords
metal
semiconductor element
protrusion
electrode
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58194626A
Other languages
Japanese (ja)
Inventor
Minoru Hirai
平井 稔
Kenzo Hatada
畑田 賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58194626A priority Critical patent/JPS6085545A/en
Publication of JPS6085545A publication Critical patent/JPS6085545A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To attach a bump electrode to a non-defective element only by a method wherein, after a bump electrode formed at the position on a substrate corresponding to the junction pad of a semiconductor element has been temporarily transferred to the tip of a group of leads, the bump electrode and the element pad are transferred to an element in a coincided form. CONSTITUTION:A metal film 7 is printed on a glass plate 7, a glass mask 9 is provided, and an Au protrusion 11 is formed on a window 10 by performing a plating. A metal fine wire 12 of 50mum in wire width is provided on a substrate in the same pitch as the protrusion 11, and an Sn plating is performed on the surface. The fine wire 12 group and the metal protrusion 11 group are positioned, heat and pressure are applied to them using a tool 13, and they are transferred and connected in a collective manner. Then, a positioning is performed on the transferred fine wire 12 and the metal electrode 15 of a semiconductor element 14, heat and pressure are applied to the above, a supersonic vibration 16 is added, and when the fine wire 12, the metal protrusion 11, and the electrode 15 of the element 14 are simultaneous connected in a collective manner, a metal protrusion only is left on the electrode 15 of the element. As a metal protrusion is provided on the non-defective element only, wastefullness can be removed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体素子上電極へ金属突起物を形成する半導
体素子への突起電極形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming a protruding electrode on a semiconductor element, which involves forming a metal protrusion on an electrode on a semiconductor element.

従来例の構成とその問題点 従来の半導体素子上電極への金属突起電極形成方法を第
1図に従って説明する。
Structure of a conventional example and its problems A conventional method of forming a metal protrusion electrode on an electrode on a semiconductor element will be explained with reference to FIG.

一般にS i02膜1上にh(l 配線2かあり、その
上に保護膜3がある。寸ずAe パレット部4より大き
めにA(? との密着力を増すためにCr+Tiなどが
数千人蒸着される。さらに突起物材であるAu の拡散
防止のだめに、Cu、Pdが数千へ蒸着される。
Generally, there is h(l wiring 2 on the Si02 film 1, and a protective film 3 on top of it. Thousands of Cr+Ti etc. are placed on the Ae pallet part 4 to increase the adhesion with the A(?). Additionally, several thousand Cu and Pd are deposited to prevent the diffusion of Au, which is the protrusion material.

これらをバリヤメタル層5という。その後、数十μ7n
Auや半田かメッキされ、金属突起物6が形成される。
These are called barrier metal layers 5. After that, several tens of μ7n
The metal protrusions 6 are formed by plating with Au or solder.

従来の金属突起物形成方法では、完成した半導体素子ウ
ェハーに、蒸着、ホトリソ、メッキなどの処理が新たに
加わる。このため、金属突起物6の形成時に良品の半導
体素子を不良にし、歩留の低下を招く恐れがある0また
、この金属突起物形成方法が1ウエハーを単位とした処
理工程であるため、ウェハー内の半導体素子の良、不良
にかかわらずその電極上に金属突起物6を形成してしま
い、歩留の低いウェノ・−では非常に効率の悪い処理工
程となってしまう0 発明の目的 本発明は半導体素子への突起電極形成方法において、形
成時に良品半導体素子を不良にする恐れの少ないまた、
不良半導体素子には、突起電極を形成することがなく、
良品半導体素子のみの電極上に突起電極を形成する方法
を提供するものであるO 発明の構成 この目的を達成するために本発明は、基板上に半導体素
子のポンディングパッドに対応した位置に形成された突
起電極を一群のリード先端へ仮転写する工程と、前記一
群のリード先端の突起電極と半導体素子のポンディング
パッドを一致させて加熱・加圧し、前記突起電極を半導
体素子へ転写接合させ、前記リード群を突起電極から離
脱する工程とからなることを特徴とするものである0実
施例の説明 本発明の一実施例を第2図〜第8図に従って説明する。
In conventional methods for forming metal protrusions, completed semiconductor device wafers undergo additional processes such as vapor deposition, photolithography, and plating. For this reason, when forming the metal protrusions 6, there is a risk that a good semiconductor element may become defective, leading to a decrease in yield.In addition, since this method of forming metal protrusions is a processing step for each wafer, the wafer Metal protrusions 6 are formed on the electrodes regardless of whether the semiconductor elements inside are good or defective, resulting in a very inefficient processing process in low-yield semiconductor devices. is a method for forming protruding electrodes on semiconductor devices, which is less likely to cause defects in good semiconductor devices during formation.
No protruding electrodes are formed on defective semiconductor elements;
This invention provides a method for forming protruding electrodes on electrodes of only non-defective semiconductor elements.Structure of the InventionIn order to achieve this object, the present invention provides a method for forming protruding electrodes on electrodes of only non-defective semiconductor elements. a step of temporarily transferring the protruding electrodes to the tips of a group of leads, and aligning the protruding electrodes of the group of lead tips with a bonding pad of a semiconductor element and applying heat and pressure to transfer and bond the protruding electrodes to the semiconductor element. Description of an Embodiment An embodiment of the present invention will be described with reference to FIGS. 2 to 8.

第1図と同一部分には同一番号を付している。まず、金
属突起物のみを形成するだめの基板の作成方法と、金属
突起物の形成方法を述べる。
The same parts as in FIG. 1 are given the same numbers. First, a method for creating a substrate on which only metal protrusions are formed and a method for forming metal protrusions will be described.

第2図、第3図でガラス板子上に、メッキ用の電極とし
て金属膜8を蒸着あるいは印刷によって形成する。さら
に、この上にメッキ時のヅスク用にガラス膜9を焼成形
成し半導体素子の電極に対応した位置にメッキ成長用窓
10をガラス膜9をエツチングして形成する。この基板
にAu メッキをほどこして窓1o上にAu 突起物1
1を形成する。
In FIGS. 2 and 3, a metal film 8 is formed as a plating electrode on a glass plate by vapor deposition or printing. Further, a glass film 9 is fired on top of the glass film 9 for use in plating, and windows 10 for plating growth are formed by etching the glass film 9 at positions corresponding to the electrodes of the semiconductor element. Au plating is applied to this board, and Au protrusion 1 is placed on window 1o.
form 1.

ガラス板7のかわりにセラミックス、Si などを用い
ても同様に金属突起物11を形成することができる。
The metal protrusions 11 can be similarly formed by using ceramics, Si, or the like instead of the glass plate 7.

次に第4図に示すように金属細線12と前記金属突起1
1とを接合する。金属細線12は基板上に形成された金
属突起物11と同ピツチで線幅50μ〃z程度で、その
表面をSn メッキしたものを使用する。
Next, as shown in FIG.
1 is joined. The thin metal wires 12 have the same pitch as the metal protrusions 11 formed on the substrate, have a line width of about 50 .mu.z, and have their surfaces plated with Sn.

第に第5図、第6図に示すように金属細線12群と基板
上の金属突起物11群とを位置合せ後、加熱ツール13
で加熱加圧することにより、金属細線12群に金属突起
物11群を同時に一括して転写接合する。
First, as shown in FIGS. 5 and 6, after aligning the 12 groups of thin metal wires and the 11 groups of metal projections on the substrate, the heating tool 13
By applying heat and pressure, the 11 groups of metal protrusions are simultaneously transferred and bonded to the 12 groups of thin metal wires.

次に、第7図に示すように下部に金属突起物11を転写
した金属細線12群と半導体素子14上で金属電極15
群とを接合する。金属突起物11群は半導体素子14上
の金属電極15群に対応した位置で基板上に形成してい
るため金属細線12群に転写後もやはり金属電極15群
に対応した位置を保っている。この金属細線12群上の
金属突起物11と半導体素子14上の金属電極15群と
を位置合せ後に、加熱ツール13によシ加熱加圧して、
金属細線12群、金属突起物11.半導体素子14上の
金属電極16群の3者を同時に一括して接合する。3者
の接合後も加熱ツールによシ加圧を続け、さらに加熱ツ
ール13に超音波振動16を付加する。超音波振動16
は3者の接合部へ伝達される。
Next, as shown in FIG.
Join the group. Since the metal protrusions 11 groups are formed on the substrate at positions corresponding to the metal electrodes 15 groups on the semiconductor element 14, they also maintain the positions corresponding to the metal electrodes 15 groups even after being transferred to the metal thin wires 12 groups. After aligning the metal protrusions 11 on the 12 groups of thin metal wires and the 15 groups of metal electrodes on the semiconductor element 14, they are heated and pressurized by the heating tool 13.
12 groups of thin metal wires, 11 metal protrusions. Three groups of metal electrodes 16 on the semiconductor element 14 are bonded together at the same time. After joining the three members, pressure is continued by the heating tool, and ultrasonic vibrations 16 are further applied to the heating tool 13. Ultrasonic vibration 16
is transmitted to the junction of the three.

そして、第8図に示すように金属突起物11と金属細線
12との接合はAu/Sn合金により行われているが、
Au%n合金は比較的もろいので、超音波振動16によ
り破壊されて金属突起物11と金属細線12は剥離する
。その結果、半導体素子14上の金属電極15上に金属
突起物11のみが残る。
As shown in FIG. 8, the metal protrusion 11 and the thin metal wire 12 are bonded using an Au/Sn alloy.
Since the Au%n alloy is relatively brittle, it is destroyed by the ultrasonic vibration 16 and the metal protrusion 11 and the metal wire 12 are separated. As a result, only the metal protrusion 11 remains on the metal electrode 15 on the semiconductor element 14.

金属突起物形成基板から、金属突起物11を半導体素子
14上の金属電極16へ転写するだめの媒体となる金属
細線12は表面のSn メッキが無くなるまで何度も使
用することができるoiた、金属突起物形成基板も、使
用後再びメッキすることにより金属突起物を形成するこ
とができる0発明の効果 本発明による半導体素子上の電極への金属突起物形成方
法では、半導体素子へ蒸着、ホトリソ。
The thin metal wire 12, which serves as a medium for transferring the metal protrusions 11 from the metal protrusion forming substrate to the metal electrode 16 on the semiconductor element 14, can be used many times until the Sn plating on the surface disappears. Metal protrusions can also be formed on the metal protrusion-forming substrate by plating it again after use. Effects of the Invention In the method of forming metal protrusions on electrodes on a semiconductor element according to the present invention, metal protrusions are formed on the semiconductor element by vapor deposition, photolithography, etc. .

メッキなどの処理が不要で、歩留の低下が防げる。Processing such as plating is not required, preventing a drop in yield.

また、良品半導体素子だけを選んで金属突起物を形成す
ることができるため、不良半導体素子へ金属突起物を形
成するという無駄がなくなり、歩留の低い半導体素子ウ
ェハーにも効率良く金属突起物形成ができるなどの利点
をもち、工業的価値の大なるものである。
In addition, since metal protrusions can be formed by selecting only good semiconductor elements, there is no need to form metal protrusions on defective semiconductor elements, and metal protrusions can be formed efficiently even on low-yield semiconductor element wafers. It has the advantage of being able to perform various functions, and is of great industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来法による金属突起物の断面図、第2図は本
発明によるガラス基板上へ形成した金属突起物の断面図
、第3図は本発明によるガラス基或した金属突起物と加
熱ツールの位置関係を示す側面図、第0図は金属細線と
金属突起物とを接合した側面図、第7図は金属細線へ転
写形成した金属突起物と半導体素子上の電極とを接合し
て、超音波振動を加えた時の側面図、第8図は金属細線
と金属突起物とが剥離し、半導体素子上の電極へ金属突
起物を形成した側面図である。 1・・・・・・SiO2膜、2・・・・・・he電極、
3・・・・・・保護膜、4・・・・・・h(l パッド
、6・・・・・・)くリアメタル層、6・・・・・・金
属突起物、7・・・・・・ガラス板、8・・・・・・金
属膜、9・・・・・・ガラス膜、10・・・・・・7ノ
キ成長用窓、11・・・・・・Au突起物、12・・・
・・・金属細線、13・・・・・加熱ツール、1−4・
・・・・・半導体素子、15・・・・・・金属電極、1
6・・・・・・超音波振動。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名@3
図 第4図 I2 第5図 第6図 7 第7図
FIG. 1 is a cross-sectional view of a metal protrusion formed by a conventional method, FIG. 2 is a cross-sectional view of a metal protrusion formed on a glass substrate according to the present invention, and FIG. 3 is a cross-sectional view of a metal protrusion formed on a glass substrate and heated by the present invention Figure 0 is a side view showing the positional relationship of the tools. Figure 0 is a side view of a thin metal wire and a metal protrusion bonded to each other. Figure 7 is a side view of a thin metal wire and a metal protrusion bonded to each other. , a side view when ultrasonic vibration is applied, and FIG. 8 is a side view in which the thin metal wire and the metal protrusion are separated and the metal protrusion is formed on the electrode on the semiconductor element. 1...SiO2 film, 2...he electrode,
3...protective film, 4...h (l pad, 6...) rear metal layer, 6...metal protrusion, 7... ...Glass plate, 8...Metal film, 9...Glass film, 10...7 Window for tree growth, 11...Au protrusion, 12 ...
...Thin metal wire, 13...Heating tool, 1-4.
... Semiconductor element, 15 ... Metal electrode, 1
6... Ultrasonic vibration. Name of agent: Patent attorney Toshio Nakao and 1 other person @3
Figure 4 Figure I2 Figure 5 Figure 6 Figure 7 Figure 7

Claims (1)

【特許請求の範囲】[Claims] (1)基板上に半導体素子のポンディングパッドに対応
した位置に形成された突起電極を一群のリード先端へ仮
転写する工程と、前記一群のIJ +ド先端の突起電極
と半導体素子のポンディングパッドを一致させて加熱・
加圧し、前記突起電極を半導体素子へ転写、接合させ、
前記リード群を突起電極から離脱する工程とからなるこ
とを特徴とする半導体素子への突起電極形成方法。 EI IJ−ドが錫メッキされたリード、突起電極が金
、ポンディングパッドがアルミを主成分とする金属であ
り、リード先端に仮転写された突起電極を加熱および超
音波を印加してポンディングパッドへ接合させ、しかる
後、接合部を加熱して前記リードを突起電極から引き離
すことを特徴とする特許請求の範囲第1項記載の半導体
素子への突起電極形成方法。
(1) Temporary transfer of protruding electrodes formed on the substrate at positions corresponding to the bonding pads of the semiconductor element to the tips of a group of leads, and bonding of the protruding electrodes at the tips of the group of IJ + leads and the semiconductor element. Match the pads to heat/
Pressure is applied to transfer and bond the protruding electrode to the semiconductor element,
A method for forming protruding electrodes on a semiconductor element, comprising the step of separating the lead group from the protruding electrodes. EI IJ- lead is tin-plated, the protruding electrode is gold, and the bonding pad is a metal whose main component is aluminum.The protruding electrode temporarily transferred to the tip of the lead is bonded by heating and applying ultrasonic waves. 2. The method of forming a protruding electrode on a semiconductor element according to claim 1, wherein the lead is bonded to a pad, and then the bonded portion is heated to separate the lead from the protruding electrode.
JP58194626A 1983-10-18 1983-10-18 Method for formation of bump electrode for semiconductor element Pending JPS6085545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58194626A JPS6085545A (en) 1983-10-18 1983-10-18 Method for formation of bump electrode for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58194626A JPS6085545A (en) 1983-10-18 1983-10-18 Method for formation of bump electrode for semiconductor element

Publications (1)

Publication Number Publication Date
JPS6085545A true JPS6085545A (en) 1985-05-15

Family

ID=16327640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58194626A Pending JPS6085545A (en) 1983-10-18 1983-10-18 Method for formation of bump electrode for semiconductor element

Country Status (1)

Country Link
JP (1) JPS6085545A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0859686A4 (en) * 1995-05-26 1998-11-11 Formfactor Inc Fabricating interconnects and tips using sacrificial substrates

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0859686A4 (en) * 1995-05-26 1998-11-11 Formfactor Inc Fabricating interconnects and tips using sacrificial substrates

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