JPS6085512A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to miniaturize both a P-channel region and an N-channel region by using wafers having a (100) crystal face as an Si substrate in heat treatment for the isothermal second in manufacture of C-MOS.LSI. CONSTITUTION:Using Si wafers having a (100) crystal face as a substrate 1, an N type well region 2 and a P type well region 3 are diffused and formed on the surface layer of the substrate respectively while they are separated by a thick SiO film. Next, an amorphous source drain region 8 consisting of BF2 ion injection layers is formed in the region 2 forming the P-channel and an amorphous source drain region 9 consisting of P ion injection layers is similarly provided in the region 3 forming the N-channel. After this, gate electrodes 5 are provided via gate oxide films 6 between the regions 8 and 9 respectively, and the whole surface of the electrodes is covered by an interlaminar insulating film 7. The regions 8 and 9 are subjected to isothermal annealing using halogen lamps or graphite heaters to activate these regions as well as recrystalize thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device. Especially 0MO
It is effective in manufacturing 8VLSI.

Conventionally, annealing of the ion-implanted layer is performed using an electric furnace, and the implanted impurities are redistributed and diffused due to the heat treatment lasting for minutes (for example, 950° C. for 30 minutes). For this reason, in the source/drain heavily doped layers of the MOS-FET, due to the diffusion of impurity ions, punch-through occurs when the gate length is shortened, making it difficult to reduce the gate length to 2 μm or less. In particular, in 0MO8LSI, B or BF is implanted into the P-channel source/drain region, which causes large transverse waves in the P-channel, source, and drain during high-temperature annealing, making LSI miniaturization and high integration adamantly discouraged. . In addition, when 88 ions are implanted into an S=wafer with a (111) crystal orientation plane・♂−p−
In order to reduce the junction leakage current of OA to about 1 nA/cd, heat treatment at 1200°C for about 8 seconds is required.
In the case of 8, the diffusion coefficient is small, so even with heat treatment at 1200°C for 8 seconds, diffusion due to redistribution of As ions is small, and 1oo
ooX, but B or BF2 has a large diffusion coefficient, and annealing at 1200° C. for 8 seconds causes diffusion due to redistribution of 2000% or more. For this reason, O'MOS
In manufacturing LSI, using a (111) oriented S<substrate, B is placed in the P channel region and A is placed in the N channel region.
The conventional method of annealing by high-temperature and short-time heat treatment after implanting s made it difficult to miniaturize MO8LSI, especially the P-channel region.The present invention compensates for such drawbacks of the conventional method. An object of the present invention is to provide a method for manufacturing a semiconductor using a low-temperature second-unit annealing technique that enables miniaturization of both N-channel regions and high integration of MO3LSI. Using (100) silicon and 13F in the P channel region,
, the N channel is characterized by forming an amorphous layer by P implantation and then annealing at a low temperature (800° C. or higher and 1100° C. or lower) in seconds.

The present invention will be explained below using examples.

FIG. 1 is a cross-sectional view of the 0M0S FET according to the present invention. The substrate 1 is made of silicon with a (100) crystal orientation, the P channel source/drain 8 regions are EF, the ion implantation layer, the N channel source, and the The drain region 9 is characterized in that a P ion implantation layer is used.

N well 2 ・P on a silicon (100) substrate
After forming well 6, separating active elements by LOOO 34, and forming gate film 5i026 and gate electrode 8ii5, B F is applied to P channel source/drain region 8.
.

P is implanted into the N channel source/drain region 9 to form a shallow amorphous layer. After accumulating the insulating PSG film 7, the ion implantation layer is recrystallized and activated by iso-thermal annealing using a halogen lamp or a graphite heater. Here, the ion-implanted amorphous layer by BF2 and the ion-implanted amorphous layer by P are formed by heating at a low temperature for a short time (e.g. 800°C) when the substrate is 5 ((1oo)).
Recrystallize and activate in 1 second).

At this time, the junction leakage current is also as small as 1 nA/cd.

FIG. 2 shows a two-dimensional space diagram for one hour of low-temperature short-time annealing according to the present invention. , shows the minimum heat treatment conditions necessary to have a junction leakage of about 1 nA, /Cd. (E)
is an annealing condition under which impurities in the BF2 or P injection layer are redistributed and diffusion begins. Therefore, by performing heat treatment at the temperature and time space shown in the shaded area in Figure 2, the sources and drains in the P-channel and N-channel regions do not diffuse, and a good junction is formed, making it possible to miniaturize both channels. Become. After annealing, CMOS is fabricated by forming contact holes and patterning AI, 10.
-FET is completed. As explained above, by using the method for manufacturing a semiconductor device according to the present invention, annealing can be performed at a low temperature and in a short time without causing diffusion due to redistribution of boron, which is an impurity in the P channel region, and phosphorus, which is an impurity in the N channel region. This makes it possible to miniaturize the P-channel and N-channel regions, resulting in highly integrated 0MO8LS.
I can provide I.

[Brief explanation of the drawing]

Figure 1: Cross-sectional view of 0MO3-FET according to the present invention Figure 2: Two-dimensional space diagram of one hour of low-temperature short-time annealing according to the present invention 1: (100) crystal Silicon substrate 2 with azimuth plane -
N well 3 - P well 4...LOO
O85...Gate electrode 6...Gate oxide film 7...Interlayer insulating film 8...BV
2 Injection layer 9...P injection layer 10...AL wiring (A)...Minimum temperature/time annealing condition necessary for recrystallization (B)/Maximum temperature/time annealing condition where source/drain impurities do not diffuse Applicant Suwa Seikosha Co., Ltd. Patent Attorney Tsutomu Mogami

Claims (1)

[Claims] 1) A method for manufacturing a semiconductor device, characterized in that a wafer having a (100) crystal orientation plane is used as the Si substrate in iso-thermal second-unit heat treatment in LSI manufacturing. 2) The method for manufacturing a semiconductor device according to claim 1, wherein the short-time heat treatment is performed using a halogen lamp or a graphite heater. 3) In the formation of source/drain regions in the manufacture of 0MO8/VLSI, in the S=substrate of the (100) crystal orientation plane, BP and ions are implanted in the P channel transistor region and the N channel transistor region. After forming an amorphous layer by implanting P ions in
The method for manufacturing a semiconductor device according to claim 1, wherein the annealing is performed in seconds at a humidity of 00° C. or less.