JPS6084854A - Resin-sealed type semiconductor device - Google Patents
Resin-sealed type semiconductor deviceInfo
- Publication number
- JPS6084854A JPS6084854A JP58191909A JP19190983A JPS6084854A JP S6084854 A JPS6084854 A JP S6084854A JP 58191909 A JP58191909 A JP 58191909A JP 19190983 A JP19190983 A JP 19190983A JP S6084854 A JPS6084854 A JP S6084854A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- film
- chip
- semiconductor chip
- cracks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術的背景〕
本発明は樹脂封止型半導体装置の改良に関し、特にチッ
プの大型化に伴って樹脂封止層やチップに頻発するクラ
ック発生等の問題への対策に係る。[Detailed Description of the Invention] [Technical Background of the Invention] The present invention relates to the improvement of resin-sealed semiconductor devices, and particularly to the problems such as cracks that frequently occur in resin-sealed layers and chips as chips become larger. related to measures.
第１図は従来の樹脂封止型半導体装置の一例を示す断面
図である。同図において、１はベッド部である。該ベッ
ド部１上には銀−エポキシ系接着剤等のマウント剤２を
介して半導体チップ３がマウントされている。この半導
体チップ３０表面に形成された内部端子は、メンディン
グワイヤ４を介してベッド部１の周囲に配設されたり−
ド５に接続されている。そして、ベッド部１．半導体ペ
レット３．？ンデイングワイヤ４およびリード５の一部
はエポキシ樹脂等の樹脂モールド層６で封止されている
。また、リード５は樹脂モールド層５の側壁から外部に
延出され、下方に折シ曲けられている。FIG. 1 is a sectional view showing an example of a conventional resin-sealed semiconductor device. In the figure, 1 is a bed section. A semiconductor chip 3 is mounted on the bed portion 1 via a mounting agent 2 such as a silver-epoxy adhesive. The internal terminals formed on the surface of the semiconductor chip 30 are arranged around the bed portion 1 via the mending wire 4.
connected to card 5. And bed part 1. Semiconductor pellet 3. ? A portion of the binding wire 4 and the lead 5 are sealed with a resin mold layer 6 such as epoxy resin. Further, the leads 5 extend outward from the side walls of the resin mold layer 5 and are bent downward.
上記従来の樹脂封止型半導体装置は第２図に示すような
リードフレームＬを用いて製造される。このリードフレ
ームヱは銅あるいはＮｉ／Ｆｅ合金等の導電性金属板を
プレス加工、エツチング加工等によって所定のノソター
ン形状としたものである。第２図のリードフレームヱで
は、外枠８によって３つの領域に区画され、夫々の領域
内に同一のパターンが形成されている。即ち、左端の単
位パターンに示すように、夫々の領域の略中夫にはベッ
ド部ｌが配置され、該ベッド部１はタイバー９１を介し
て外枠８に連結され、支持されている。ベッド部ｌの周
囲には多数のリード５・・・がベッド部を収り囲んで配
設され、該リード５・・・は夫々外枠８に連結されてい
る。The conventional resin-sealed semiconductor device described above is manufactured using a lead frame L as shown in FIG. This lead frame is made of a conductive metal plate made of copper or Ni/Fe alloy, etc., formed into a predetermined nosoturn shape by pressing, etching, or the like. The lead frame shown in FIG. 2 is divided into three regions by an outer frame 8, and the same pattern is formed in each region. That is, as shown in the unit pattern at the left end, a bed portion 1 is arranged approximately at the center of each region, and the bed portion 1 is connected to and supported by the outer frame 8 via tie bars 91. A large number of leads 5 are disposed around the bed l, enclosing the bed, and each of the leads 5 is connected to an outer frame 8.
また、同じ方向に延出されるリード５・・・はタイバー
９２で連結され、該タイバー９２は外枠８に連結されて
いる。このタイバー９２を境にして、リード５・・・は
内部リード５１と外部リード５２とに分けられている。Further, the leads 5 extending in the same direction are connected by tie bars 92, and the tie bars 92 are connected to the outer frame 8. The leads 5 are divided into an internal lead 51 and an external lead 52 with this tie bar 92 as a boundary.
第２図のリードフレームによシ第１図の樹脂封止型半導
体装置を製造するには、まず第２図における中間の単位
パターンに示したように、ベッド部１上に半導体チップ
３をマウントする。To manufacture the resin-sealed semiconductor device shown in FIG. 1 using the lead frame shown in FIG. 2, first mount the semiconductor chip 3 on the bed portion 1 as shown in the middle unit pattern in FIG. do.
続いて、？ンディングワイヤ４で７げンデイングノヤツ
ドと内部リード５□の先端部との間を接続した後、右端
の単位・母ターンに示すように所定領域を樹脂モールド
層６で封止する。次に、タイバー９１．９２を切除する
と共に、外部リード５□を外枠８から切シ離した後、分
離された夫々の外部リード５２を所定方向に折シ曲げれ
ば第１図の構造をもった樹脂封止型半導体装置が得られ
る。continue,? After connecting the end portion of the 7-ending wire 4 and the tip of the internal lead 5□, a predetermined area is sealed with a resin mold layer 6 as shown in the unit/mother turn at the right end. Next, after cutting out the tie bars 91 and 92 and separating the external leads 5□ from the outer frame 8, the structure shown in FIG. 1 can be obtained by bending each separated external lead 52 in a predetermined direction. A fully resin-sealed semiconductor device is obtained.
〔背景技術の１４１１題点〕
上記第１図の構造を有する従来の樹脂封止型半導体装置
では、樹脂モールド層６の所定の外形に対して塔載され
る半導体チップ３が大型化されるに伴い、半導体チップ
３および樹脂モールド層６に加わる応力が大きくなシ、
クラック発生等、次のような種々の問題が顕著に現われ
るに至ったＯ
第１に、樹脂モールド層６に発生するクラックの問題が
挙げられる。これは樹脂モールド層６とリードフレーム
７（特にベッド部１）および半導体チップ３との間に生
じる応力に起因するものであるが、チップの大型化に伴
って樹脂モールド層、６の強度が相対的に低下するため
、クラックを生じ易くなっている。[Problem 1411 of Background Art] In the conventional resin-molded semiconductor device having the structure shown in FIG. Accordingly, the stress applied to the semiconductor chip 3 and the resin mold layer 6 is large.
The following various problems such as the occurrence of cracks have become conspicuous. First, there is the problem of cracks occurring in the resin mold layer 6. This is due to the stress generated between the resin mold layer 6, the lead frame 7 (particularly the bed part 1), and the semiconductor chip 3, but as the chip becomes larger, the strength of the resin mold layer 6 becomes relatively smaller. As a result, cracks are more likely to occur.
第２の問題は半導体チップ３に生じるクラックである。The second problem is cracks that occur in the semiconductor chip 3.
この要因としては、ベッド部１と半導体チップ３との間
の熱膨張差によって生じる応力、樹脂モールド層６の収
縮により半導体チップ３の側面から加わる応力の二つが
挙げられる。この要因のうち、ベッド部１との間に生じ
る応力は半導体テップ３が大型化するほど大きくなり、
従ってクラックが発生し易くなる。This is caused by two factors: stress caused by a difference in thermal expansion between the bed portion 1 and the semiconductor chip 3, and stress applied from the side surface of the semiconductor chip 3 due to contraction of the resin mold layer 6. Among these factors, the stress generated between the semiconductor tip 3 and the bed portion 1 increases as the semiconductor tip 3 becomes larger.
Therefore, cracks are more likely to occur.
第３の問題は、半導体テップ３の表面に加わる樹脂応力
によって、チッｆ３０表層に形成されているパッシベー
ション膜にクラックが生じたり、アルミニウム配線層が
スライドしたりすることである。半導“体チップ３が大
型化すれば前記樹脂応力も大きくなるから、この問題も
チップ３の大型化に伴って顕在化することになる。The third problem is that the resin stress applied to the surface of the semiconductor chip 3 causes cracks in the passivation film formed on the surface layer of the chip f30 and causes the aluminum wiring layer to slide. As the size of the semiconductor chip 3 increases, the resin stress also increases, so this problem also becomes more apparent as the size of the chip 3 increases.
上記の問題は、実際には種々の要因が複雑に関連し合っ
て発現するもので、通常は熱衝撃試験において繰９返し
加えられる熱疲労によシ発現し、検出される場合が多い
。The above-mentioned problem actually occurs due to a complex interaction of various factors, and is usually caused by thermal fatigue that is repeatedly applied in a thermal shock test, and is often detected.
また、一つの問題を解決しようとすると他の問題が顕著
に現われることも多い。例えば上記樹脂クラックに関す
る第１の問題を改善するために樹脂モールド層の強度を
上げたり、応力分散を図ると、半導体テップ３の側面に
加わる樹脂の収納応力が大きくな９、チップ３のクララ
ｐ 、 ノ４ツクベージ膜のクラック、アルミニウム配
線層のスライドといった問題が顕著になる傾向がある。Furthermore, when trying to solve one problem, other problems often become apparent. For example, if the strength of the resin mold layer is increased or the stress is distributed in order to improve the first problem related to resin cracks, the resin storage stress applied to the side surface of the semiconductor chip 3 becomes large. , problems such as cracks in the substrate film and sliding of the aluminum wiring layer tend to become more prominent.
本発明は上記事情に鑑みてなされたもので、半導体チッ
プの大型化に伴って顕在化してまた前記種々の問題、即
ち、樹脂クラック、チップクラック、ハッシペーション
膜クラックおよびアルミニウム配線層のスライドの問題
を何れも抑制し、信頼性を向上することができる樹脂封
正型半導体装置を提供するものである。The present invention has been made in view of the above-mentioned circumstances, and the various problems mentioned above have become apparent with the increase in the size of semiconductor chips, namely, resin cracks, chip cracks, hashipation film cracks, and sliding problems of aluminum wiring layers. The object of the present invention is to provide a resin-sealed semiconductor device that can suppress both of these problems and improve reliability.
本発明は次の二つの技術手段からなっている。 The present invention consists of the following two technical means.
第１は、従来の樹脂封止型半導体装置において半導体チ
ップにクラックを生じる主な要因であった、ベッド部と
の熱膨張差に起因する応力をなくすだめの手段である。The first is a means for eliminating stress caused by a difference in thermal expansion with the bed portion, which was the main cause of cracks in semiconductor chips in conventional resin-sealed semiconductor devices.
即ち、本発明では従来の金属性のベッド部を廃止し、代
シにフレキシブルな絶縁フィルム、例えばポリイミド樹
脂フィルム上に半導体イレットをマウントさせる手段を
採用する。That is, in the present invention, the conventional metal bed part is abolished, and instead a means for mounting the semiconductor islet on a flexible insulating film, such as a polyimide resin film, is adopted.
なお、樹脂モールド層のクラックは、従来ベッド部周縁
に沿って発生する場合が多かりたから、この第１の手段
は樹脂モールド層のクラックを防止する上でも有効な手
段となる。Incidentally, since cracks in the resin mold layer conventionally often occur along the periphery of the bed portion, this first means is also an effective means for preventing cracks in the resin mold layer.
本発明における第２の技術手段は、前記フレキシブルな
絶縁フィルム上に前記半導体チップを取シ囲む絶縁枠体
を配置することである。この第２の技術手段は樹脂モー
ルド層の収縮により生じる応力を食い止め、該応力が半
導体テップに側面方向から加わるのを防止する作用を果
たし、半導体チップのクラックを防止すると共にパ、シ
ペーション膜のクラック発生およびアルミニウム配線の
スライドを防止する。A second technical means of the present invention is to arrange an insulating frame surrounding the semiconductor chip on the flexible insulating film. This second technical means suppresses the stress caused by the contraction of the resin mold layer and prevents the stress from being applied to the semiconductor chip from the side, thereby preventing cracks in the semiconductor chip and cracks in the persipation film. Prevents occurrence and sliding of aluminum wiring.
本発明にあっては前記第１および第２の二つの技術手段
が相俟って所期の目的を達成するものである。特に、前
記第１の手段を採用して従来のベッド部を廃止すると、
樹脂モールドＪ−の収縮による応力がまともに半導体チ
ップに加わることによるから、これによるチップクラッ
ク等の間穐を防止するために前記第２の手段を併用する
ことが不可欠となる。In the present invention, the first and second technical means described above work together to achieve the intended purpose. In particular, if the first means is adopted and the conventional bed section is abolished,
Since the stress caused by the shrinkage of the resin mold J- is directly applied to the semiconductor chip, it is essential to use the second means in combination to prevent chip cracks and the like caused by this.
なお、本発明における前記フレキシブルな絶縁性フィル
ムとしては、ポリイミドフィルムの他にもポリエステル
フィルム等を用いることができる。In addition, as the flexible insulating film in the present invention, a polyester film or the like can be used in addition to the polyimide film.
また、前記絶縁枠体として゛はシリコーン２バー、ウレ
タンラバー等の弾性を有するもの、あるいはセラミック
ス等の剛性の高いものの何れを用いてもよい。ただし、
弾性絶縁体を用いる方がよシ望ましい。The insulating frame may be made of an elastic material such as silicone bar or urethane rubber, or a highly rigid material such as ceramics. however,
It is better to use elastic insulators.
以下、第３図を参照して本発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to FIG.
第３図は本発明の一実施例になる樹脂封止型半導体装置
の断面図である。同図において、Ｉノはポリイミド樹脂
フィルムである。該ポリイミド樹脂フィルムＪＪ上には
マウント剤１２を介し７て半導体チップ１３がマウント
されている。該半導体テップ１３を取り囲む７リコンラ
バー製の絶縁枠体１４が前記ポリイミド樹脂フィルム１
１上に配賦されている。また、絶縁枠体１４の外側には
リード１５・・・がその一端部を前記ポリイミド樹脂フ
ィルム１１上に固定して配置され、該リード１５・・・
の一端部はポンディングワイヤ１６を介して前記半導体
テップ１３の表面に形成された内部端子に接続されてい
る。FIG. 3 is a sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention. In the figure, I is a polyimide resin film. A semiconductor chip 13 is mounted on the polyimide resin film JJ with a mounting agent 12 interposed therebetween. An insulating frame 14 made of silicone rubber surrounding the semiconductor chip 13 is made of the polyimide resin film 1.
It is allocated on top of 1. Furthermore, leads 15 are arranged outside the insulating frame 14 with one end thereof fixed on the polyimide resin film 11, and the leads 15 are arranged with one end thereof fixed on the polyimide resin film 11.
One end of the semiconductor chip 13 is connected to an internal terminal formed on the surface of the semiconductor chip 13 via a bonding wire 16.
そして、前記ポリイミド樹脂フィルム１ノ、半導体テッ
プ０１３．絶縁枠体１４．？ンデイングワイヤ１６およ
びリード１５の一端部は樹脂モールド層１７によシ封止
されている。更に、前記リード１５の他端部は樹脂モー
ルド層１７から外方に延出され、下向に向けて折り曲げ
られている。Then, the polyimide resin film 1 and the semiconductor tape 013. Insulating frame 14. ? One end of the binding wire 16 and the lead 15 is sealed with a resin mold layer 17. Furthermore, the other end of the lead 15 extends outward from the resin mold layer 17 and is bent downward.
上記構造からなる樹脂封止型半導体装置では、半導体チ
ップ１３のマウントされているポリイミド樹脂フィルム
１１が従来の金属製ベッド部に比べて遥かにフレキシブ
ルである。このため、両者の熱膨張差により半導体チッ
プ１３に加わる応力は従来よりも著しく軽減され、テッ
プ１３のクラック発生を防止できる。同時に、従来ベッ
ド部の周縁に沿って発生していｆｃｌ（脂モールド層１
７のクラックも防止される。In the resin-sealed semiconductor device having the above structure, the polyimide resin film 11 on which the semiconductor chip 13 is mounted is much more flexible than the conventional metal bed portion. Therefore, the stress applied to the semiconductor chip 13 due to the difference in thermal expansion between the two is significantly reduced compared to the conventional case, and the occurrence of cracks in the tip 13 can be prevented. At the same time, fcl (fatty mold layer 1
7 cracks are also prevented.
また、シリコーンラバー製の絶縁枠体１４が配設されて
いるため、樹脂モールド層１７の収縮によって半導体チ
ップ１３の側面から加わる応力が吸収され、半導体チッ
プＪ３に直接加わる応力は著しく軽減される。従って、
この応力に起因するチップクラック、）９ツシベーシヨ
ン膜のクラック、アルミニウム配線層のスライド等の問
題を回避することができる。Further, since the insulating frame 14 made of silicone rubber is provided, the stress applied from the side surface of the semiconductor chip 13 due to contraction of the resin mold layer 17 is absorbed, and the stress directly applied to the semiconductor chip J3 is significantly reduced. Therefore,
Problems such as chip cracks, cracks in the insulation film, and sliding of the aluminum wiring layer caused by this stress can be avoided.
なお、上記実施例の樹脂封止型半導体装置は次のように
して製造することができる。Note that the resin-sealed semiconductor device of the above embodiment can be manufactured as follows.
まず、第２図で説明したようなリードフレーム（但し、
ベッド部１のないもの）を用意し、所定寸法の？リイミ
ド樹脂フィルムをインナーリード５１の裏面に接着剤等
で固定する。次いで、絶縁枠体をインナーリード５１の
先端よりも内側に位置するようにポリイミド樹脂フィル
ム上に固着した後、該絶縁枠体で囲まれたポリイミド樹
脂フィルム上に半導体チップをマウンなえば第３図の構
造をもった樹脂封止型半導体装置が得られる。First, the lead frame as explained in Fig. 2 (however,
Prepare a bed (without bed part 1) and use it with the specified dimensions. A reimide resin film is fixed to the back surface of the inner lead 51 with an adhesive or the like. Next, the insulating frame is fixed onto the polyimide resin film so as to be located inside the tips of the inner leads 51, and then the semiconductor chip is mounted on the polyimide resin film surrounded by the insulating frame as shown in FIG. A resin-sealed semiconductor device having the structure is obtained.
以上詳述したように、本発明によれば半導体チップの大
型化に伴って顕在化して来た樹脂クラック、チップクラ
ック、パッシベーション膜クラック、アルミニウム配線
層のスライドといった問題を何れも顕著に抑制した信頼
性の高い樹脂封止型半導体装置を提供できるものである
。As described in detail above, according to the present invention, problems such as resin cracks, chip cracks, passivation film cracks, and aluminum wiring layer sliding, which have become apparent as semiconductor chips have become larger, have been significantly suppressed. Accordingly, it is possible to provide a resin-sealed semiconductor device with high performance.
第１図は従来の樹脂封止型半導体装置の断面図、第２図
は第１図の樹脂封止型半導体装置の製造に用いられるリ
ードフレームと、これを用いた樹脂封止型半導体装置の
製造工程を説明するための平面図、第３図は本発明の一
実施例になる樹脂封止型半導体装置を示す断面図である
。
１１・・・ポリイミド樹脂フィルム、１２・・・マウン
ト剤、１３・・・半導体チップ、１４・・・絶縁枠体、
Ｊ５・・・リード、１６・・・ポンディングワイヤ、１
７・・・樹脂モールド層。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図
コ２ ｂｌ ８
第３図Fig. 1 is a cross-sectional view of a conventional resin-sealed semiconductor device, and Fig. 2 shows a lead frame used in manufacturing the resin-sealed semiconductor device shown in Fig. 1, and a lead frame of a resin-sealed semiconductor device using this lead frame. FIG. 3 is a plan view for explaining the manufacturing process, and a cross-sectional view showing a resin-sealed semiconductor device according to an embodiment of the present invention. 11... Polyimide resin film, 12... Mounting agent, 13... Semiconductor chip, 14... Insulating frame,
J5...Lead, 16...Ponding wire, 1
7...Resin mold layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Co2 bl 8 Figure 3
Claims (1)
体チップと、該半導体チップから離間してその周囲に配
設され、かつ端部を前記絶縁性フィルム上に接着された
複数のリードと、該リードの端部と前記半導体チップの
間で半導体チップを取り囲んで配設され、かつ前記絶縁
性フィルム上に固定された絶縁枠体と、前記リードの端
部と前記半導体チップ表面の内部端子との間を接続する
ビンディングワイヤと、前記絶縁性フィルム、半導体チ
ップ、リード、絶縁枠体およびボンディングワイヤ・を
封止する樹脂モールド層とを具備し、前記複数のリード
の他端部が樹脂モールド層から外方に延出されているこ
とを特徴とする樹脂封止型半導体装置。A semiconductor chip mounted on a flexible insulating film, a plurality of leads arranged around the semiconductor chip at a distance from the semiconductor chip, and having ends glued onto the insulating film, and ends of the leads. an insulating frame disposed surrounding the semiconductor chip between the lead and the semiconductor chip and fixed on the insulating film, and an end of the lead and an internal terminal on the surface of the semiconductor chip. and a resin mold layer that seals the insulating film, the semiconductor chip, the leads, the insulating frame, and the bonding wire, the other ends of the plurality of leads extending outward from the resin mold layer. A resin-sealed semiconductor device characterized in that it is extended.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191909A JPS6084854A (en) | 1983-10-14 | 1983-10-14 | Resin-sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191909A JPS6084854A (en) | 1983-10-14 | 1983-10-14 | Resin-sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6084854A true JPS6084854A (en) | 1985-05-14 |
Family
ID=16282463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58191909A Pending JPS6084854A (en) | 1983-10-14 | 1983-10-14 | Resin-sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6084854A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1988006348A1 (en) * | 1987-02-20 | 1988-08-25 | Lsi Logic Corporation | Integrated circuit package assembly |
| US5249354A (en) * | 1991-09-25 | 1993-10-05 | American Telephone & Telegraph Co. | Method of making electronic component packages |
| EP0314707B1 (en) * | 1987-05-13 | 1994-10-05 | Lsi Logic Corporation | Wire bonds and electrical contacts of an integrated circuit device |
| US5408127A (en) * | 1994-03-21 | 1995-04-18 | National Semiconductor Corporation | Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components |
| US5409863A (en) * | 1993-02-19 | 1995-04-25 | Lsi Logic Corporation | Method and apparatus for controlling adhesive spreading when attaching an integrated circuit die |
| US5428885A (en) * | 1989-01-14 | 1995-07-04 | Tdk Corporation | Method of making a multilayer hybrid circuit |
-
1983
- 1983-10-14 JP JP58191909A patent/JPS6084854A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1988006348A1 (en) * | 1987-02-20 | 1988-08-25 | Lsi Logic Corporation | Integrated circuit package assembly |
| EP0314707B1 (en) * | 1987-05-13 | 1994-10-05 | Lsi Logic Corporation | Wire bonds and electrical contacts of an integrated circuit device |
| US5428885A (en) * | 1989-01-14 | 1995-07-04 | Tdk Corporation | Method of making a multilayer hybrid circuit |
| US5249354A (en) * | 1991-09-25 | 1993-10-05 | American Telephone & Telegraph Co. | Method of making electronic component packages |
| US5409863A (en) * | 1993-02-19 | 1995-04-25 | Lsi Logic Corporation | Method and apparatus for controlling adhesive spreading when attaching an integrated circuit die |
| US5408127A (en) * | 1994-03-21 | 1995-04-18 | National Semiconductor Corporation | Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components |
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