JPS6083242U - 電子回路素子 - Google Patents
電子回路素子Info
- Publication number
- JPS6083242U JPS6083242U JP17716883U JP17716883U JPS6083242U JP S6083242 U JPS6083242 U JP S6083242U JP 17716883 U JP17716883 U JP 17716883U JP 17716883 U JP17716883 U JP 17716883U JP S6083242 U JPS6083242 U JP S6083242U
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- circuit element
- frame
- vertical piece
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第１図は従来例の断面図、第２図ａ、 ｂは同上の平面
図、第３図ａ、 ｂは本考案の一実施例の正断面図と平
面図、第４図は同上におけるフレームの斜視図、第５図
ａ、 ｂはフレームの正断面図と平面図である。 １はフレーム、２は枠状立片、３はチップ、４は接着剤
、５は開口である。
図、第３図ａ、 ｂは本考案の一実施例の正断面図と平
面図、第４図は同上におけるフレームの斜視図、第５図
ａ、 ｂはフレームの正断面図と平面図である。 １はフレーム、２は枠状立片、３はチップ、４は接着剤
、５は開口である。
Claims (2)
- （１）フレームの表面に枠状立片を突設し、この枠状立
片内にてフレームの表面にチップを接着剤で接着して成
る電子回路素子。 - （２）枠状立片の隅部は開口となっていることを特徴と
する実用新案登録請求の範囲第１項記載の電子回路素子
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17716883U JPS6083242U (ja) | 1983-11-15 | 1983-11-15 | 電子回路素子 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17716883U JPS6083242U (ja) | 1983-11-15 | 1983-11-15 | 電子回路素子 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6083242U true JPS6083242U (ja) | 1985-06-08 |
Family
ID=30384976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17716883U Pending JPS6083242U (ja) | 1983-11-15 | 1983-11-15 | 電子回路素子 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6083242U (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6322747U (ja) * | 1986-07-30 | 1988-02-15 | ||
| JPH02310213A (ja) * | 1989-05-25 | 1990-12-26 | Matsushita Electric Works Ltd | 平板瓦の梱包体の段積み方法 |
-
1983
- 1983-11-15 JP JP17716883U patent/JPS6083242U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6322747U (ja) * | 1986-07-30 | 1988-02-15 | ||
| JPH02310213A (ja) * | 1989-05-25 | 1990-12-26 | Matsushita Electric Works Ltd | 平板瓦の梱包体の段積み方法 |
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