JPS6080235A - Method of forming thin film or thick film pattern - Google Patents

Method of forming thin film or thick film pattern

Info

Publication number
JPS6080235A
JPS6080235A JP18781983A JP18781983A JPS6080235A JP S6080235 A JPS6080235 A JP S6080235A JP 18781983 A JP18781983 A JP 18781983A JP 18781983 A JP18781983 A JP 18781983A JP S6080235 A JPS6080235 A JP S6080235A
Authority
JP
Japan
Prior art keywords
pattern
thick film
substrate
thin film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18781983A
Other languages
Japanese (ja)
Other versions
JPS6246982B2 (en
Inventor
Hisashi Oguro
小黒 寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP18781983A priority Critical patent/JPS6080235A/en
Publication of JPS6080235A publication Critical patent/JPS6080235A/en
Publication of JPS6246982B2 publication Critical patent/JPS6246982B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks

Abstract

PURPOSE:To accurately detect pin holes within a pattern by coating the substrate with a fluorescent paint prior to formation of circuit pattern and irradiating such pattern with ultraviolet ray after formation of such pattern. CONSTITUTION:A fluorescent material layer 2 is formed by coating the entire part of surface of insulated ceramic substrate 1 with a fluorescent paint. Next, a gold pattern 3 is deposited thereon. The pattern 3 is irradiated with the ultraviolet ray 4 and the light emitting condition of gold pattern 3 is observed. Existence of pin hole 5 can be recognized by detecting the light emitting part in the pattern 3 and moreover pattern is corrected by coating of the gold paste 6, etc. Thereby, the failure such as disconnection can be detected easily and accurately immediately after formation of pattern.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、基板上への薄膜あるいは厚膜パターンの形成
方法に係り、特に基板上における回路パターンを構成す
る厚膜中または薄膜中のピンホールを正しく検出するた
めの方法に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for forming a thin film or a thick film pattern on a substrate, and particularly relates to a method for forming a thin film or a thick film pattern on a substrate, and in particular a method for forming a pin in a thick film or a thin film constituting a circuit pattern on a substrate. Concerning a method for correctly detecting holes.

〔従来技術〕[Prior art]

近年、装置の小型化への要求から、回路の集積化が大幅
に進められてきている。基板上に厚膜印刷を施して形成
される厚膜基板と、基板の全面に、蒸着法等によって着
膜された薄膜をフォトリソグラフィーによって所定形状
にパターニングするこ1、:よ、ヤヮされ6薄膜基a%
集積、路基板。1流となっている。
In recent years, due to the demand for miniaturization of devices, the integration of circuits has been significantly advanced. A thick film substrate is formed by thick film printing on the substrate, and a thin film deposited on the entire surface of the substrate by a vapor deposition method is patterned into a predetermined shape by photolithography. Thin film base a%
Integrated, road board. It is first class.

通常、これらの基板上の導体層のピンホール検出は、顕
微鏡を用いて行われている。しかしながら、反射光によ
る検査ではピンホールの検出は困難であり、見過してし
まうことが多く、更にこの上に絶縁層あるいは他の導体
層等の形成を行い、所望の回路基板を完成させたのちに
行われる電気的検査によってピンホール等に起因する断
線不良等が検出されることがある。この場合、すでに、
該導体層上に絶縁層を形成した仕であるから修正は不可
能であり、回路基板自体が不良品となってしまうという
不都合がありた。
Pinhole detection in conductor layers on these substrates is usually performed using a microscope. However, it is difficult to detect pinholes when inspecting using reflected light, and they are often overlooked.In addition, an insulating layer or other conductive layer is formed on top of the pinholes to complete the desired circuit board. An electrical inspection performed later may detect a disconnection defect caused by a pinhole or the like. In this case, already
Since the insulating layer is formed on the conductor layer, it is impossible to make any corrections, and there is a problem that the circuit board itself becomes a defective product.

〔発明の目的〕[Purpose of the invention]

本発明は、前記実情に鑑みてなされたもので、パターン
内のピンホールの検出を確実にし、信頼性の高い薄膜あ
るいは厚膜回路を提供することを目的とする。
The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a thin film or thick film circuit with high reliability by ensuring the detection of pinholes in a pattern.

〔発明の構成〕[Structure of the invention]

前記目的を達成するため、本発明の薄膜および厚膜パタ
ーンの形成方法は、所定の回路パターンの形成に先立ち
、基板上番と蛍光塗料を塗布しておき、該パターン形成
後、該パターンの上から紫外線を照射し、パターン内ζ
こおける発光状態を検知することによりピンホールの検
出を行うことを特徴とするものである。
In order to achieve the above object, the method for forming thin film and thick film patterns of the present invention involves coating the top of the substrate with a fluorescent paint prior to forming a predetermined circuit pattern, and after forming the pattern, UV rays are irradiated from the inside of the pattern.
This device is characterized in that pinholes are detected by detecting the light emitting state in the holes.

すなわち、回路パターンの形成工程中、すなわち、薄膜
又は厚膜の形成工程あるいはフォトエツチング工程等に
おいて形成パターン内にピンホールが発生した場合、あ
らかじめ基板上に塗布しておいた蛍光塗料が紫外線の照
射によって発光するため、ピンホールの検出が確実かつ
容易となるわけである。
In other words, if a pinhole occurs in the circuit pattern during the process of forming a circuit pattern, i.e., during the process of forming a thin film or thick film, or the photo-etching process, the fluorescent paint that has been applied on the substrate in advance may be exposed to ultraviolet rays. This makes pinhole detection reliable and easy.

〔実施例〕 以下、本発明の基板上への厚膜集積回路パターンの形成
方法について、実施例に基づき、図面を参照しつつ説明
する。
[Example] Hereinafter, a method of forming a thick film integrated circuit pattern on a substrate according to the present invention will be described based on an example with reference to the drawings.

次に示すのは、絶縁性のセラミック基板上に厚膜法によ
って、金の厚膜回路パターンを形成するだめの方法であ
る。
The following is a method for forming a gold thick film circuit pattern on an insulating ceramic substrate by a thick film method.

まず、第1図に示す如く、絶縁性のセラミック基板1の
表面全体にスプレー法によって蛍光塗料を塗布すること
により蛍光体層2を形成する。
First, as shown in FIG. 1, a phosphor layer 2 is formed by applying a fluorescent paint to the entire surface of an insulating ceramic substrate 1 by a spray method.

こののち、インクとして金ペーストを使用し、スクリー
ン印刷法によって金パターン3を第2図に示す如く着膜
形成する。
Thereafter, a gold pattern 3 is deposited as shown in FIG. 2 by screen printing using gold paste as ink.

次いで、第3図ζこ示ず如く、光源(図示せず)から、
前記金パターン3上に紫外線4を照射し、金パターン3
上の発光状態を観察する。
Next, as shown in FIG. 3, from a light source (not shown),
The gold pattern 3 is irradiated with ultraviolet rays 4, and the gold pattern 3 is
Observe the state of light emission above.

このようにして金パターン3内の発光部分を検出するこ
とにより、ピンホール5の存在を認識し、更に、第4図
ζこ示す如く、金ペースト6等を塗布することによりて
パターンの修正を行う。
By detecting the light-emitting portion within the gold pattern 3 in this manner, the existence of the pinhole 5 is recognized, and the pattern is further corrected by applying gold paste 6 or the like as shown in FIG. conduct.

続いて、絶縁層の形成さらに導体層の形成等を繰り返す
ことにより、第5図に示す如く厚膜多層配線基板が完成
される。
Subsequently, by repeating the formation of an insulating layer and a conductor layer, a thick film multilayer wiring board is completed as shown in FIG.

上述の如く、ピンホールの検出工程を導入することによ
り、ピンホールの検出が容易でかつ確実となり、断線不
良等の欠陥発生率が大幅に低下し、信頼性の高い回路基
板を得ることができる。
As mentioned above, by introducing the pinhole detection process, pinholes can be detected easily and reliably, the incidence of defects such as disconnections can be significantly reduced, and a highly reliable circuit board can be obtained. .

また、第1Wlである金パターンを形成した時点で欠陥
の発生を確実に検出できるため、欠陥を見過したまま、
次の層を形成してしすい、修正が困難となったり、修正
が不能となったりすることもない。
In addition, since the occurrence of defects can be reliably detected at the time the gold pattern, which is the first Wl, is formed, defects can be overlooked and
It is not easy to form the next layer, making it difficult or impossible to modify.

なお、実施例においては、蛍光塗料を基板表面に塗布す
るにあたり、スプレー法を用いたが、必ずしもこれに限
定されることなく、成体状の蛍光塗料を塗布する方法等
、他のいかなる方法によっても有効である。
In addition, in the examples, a spray method was used to apply the fluorescent paint to the substrate surface, but the method is not necessarily limited to this, and any other method may be used, such as a method of applying a fluorescent paint in the form of an adult. It is valid.

また、実施例においては厚膜集積回路パターンの形成l
こついて述べたが、集積回路に限らず、今一マルヘッド
等の素子基板をはじめ印刷配線基板ζこ至るまで、全て
の厚膜、薄膜回路パターンの形成に際しても、全く同様
に、本発明の方法が適用可能であることは言うまでもな
い。
In addition, in the embodiment, the formation of a thick film integrated circuit pattern is described.
As mentioned above, the method of the present invention can be applied in exactly the same manner to the formation of all thick film and thin film circuit patterns, not only for integrated circuits, but also for element substrates such as multi-heads and printed wiring boards. Needless to say, is applicable.

〔発明の効果〕〔Effect of the invention〕

以上、説明してきたように、本発明の方法によれば、所
定の回路パターンの形成に先立ち、あらかじめ基板表面
に蛍光塗料を塗布する工程と、該パターン形成後、該パ
ターンの上から紫外線を照射し、パターン白化おける蛍
光塗料の発光状態を検知することにより、ピンホールの
発生の有無を検出する工程とを含むことにより、断線不
良等の検出が該パターンの形成直後に極めて簡単に行い
得かつ確実であるため、信頼性の高い薄膜あるいは厚膜
パターンの形成が可能となる。
As explained above, according to the method of the present invention, prior to forming a predetermined circuit pattern, there is a step of applying fluorescent paint to the surface of the substrate in advance, and after forming the pattern, irradiating ultraviolet rays from above the pattern. However, by including the step of detecting the presence or absence of pinholes by detecting the luminescent state of the fluorescent paint in the pattern whitening, detection of disconnection defects etc. can be extremely easily performed immediately after the pattern is formed. Since it is reliable, it is possible to form highly reliable thin film or thick film patterns.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は、本発明実施例の方法によって、厚
膜多層配線基板を形成するための製造工程の一部を示す
図、第5図は、本発明実施例の方法によって形成された
厚膜多層配線基板を示す図である。 1・・・基板、2・蛍光体層、3・・・金パターン、4
・・紫外線、5・・ピンボール、6・・金ペースト。 第1図 第2図 第4因 a5図
1 to 4 are diagrams showing a part of the manufacturing process for forming a thick film multilayer wiring board by the method of the embodiment of the present invention, and FIG. FIG. 2 is a diagram showing a thick film multilayer wiring board. 1... Substrate, 2. Phosphor layer, 3... Gold pattern, 4
...Ultraviolet light, 5.Pinball, 6.Gold paste. Figure 1 Figure 2 Figure 4 Factor a5 Figure

Claims (1)

【特許請求の範囲】[Claims] 基板上への薄膜あるいは厚膜パターンの形成方法であっ
て、パターンの形成に先立ち、基板上に蛍光塗料を塗布
する工程と、所定の方法によって薄膜又は厚膜パターン
を形成した後、該パターン上に紫外線を照射し、パター
ン内における発光状況を検知することにより、パターン
内のピンホールの発生を検出するための工程とを含むこ
とを特徴とする基板上への薄膜あるいは厚膜パターンの
形成方法。
A method for forming a thin film or thick film pattern on a substrate, which includes a step of applying fluorescent paint on the substrate before forming the pattern, and a step of forming the thin film or thick film pattern by a predetermined method, and then applying a fluorescent paint on the pattern. A method for forming a thin film or thick film pattern on a substrate, the method comprising the step of: detecting the occurrence of pinholes in the pattern by irradiating ultraviolet rays onto the surface of the pattern and detecting the state of light emitted within the pattern. .
JP18781983A 1983-10-07 1983-10-07 Method of forming thin film or thick film pattern Granted JPS6080235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18781983A JPS6080235A (en) 1983-10-07 1983-10-07 Method of forming thin film or thick film pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18781983A JPS6080235A (en) 1983-10-07 1983-10-07 Method of forming thin film or thick film pattern

Publications (2)

Publication Number Publication Date
JPS6080235A true JPS6080235A (en) 1985-05-08
JPS6246982B2 JPS6246982B2 (en) 1987-10-06

Family

ID=16212788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18781983A Granted JPS6080235A (en) 1983-10-07 1983-10-07 Method of forming thin film or thick film pattern

Country Status (1)

Country Link
JP (1) JPS6080235A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61278737A (en) * 1985-06-03 1986-12-09 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of detecting defect in thin-film on fluorescent substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61278737A (en) * 1985-06-03 1986-12-09 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of detecting defect in thin-film on fluorescent substrate

Also Published As

Publication number Publication date
JPS6246982B2 (en) 1987-10-06

Similar Documents

Publication Publication Date Title
US20070087457A1 (en) Method for inspecting and mending defect of photo-resist and manufacturing process of printed circuit board
US3808434A (en) Method of detecting flaws in plated-through-holes of circuit modules using ultraviolet light
US5776662A (en) Method for fabricating a chip carrier with migration barrier, and resulating chip carrier
JP3070027B2 (en) Manufacturing method of wiring board
JPS6080235A (en) Method of forming thin film or thick film pattern
JPH05299793A (en) Printed wiring board
JPH05259615A (en) Formation of circuit conductor
US5234745A (en) Method of forming an insulating layer on a printed circuit board
KR20040046194A (en) pattern inspector structure of circuit board
JPS5850437B2 (en) Multilayer wiring board manufacturing method
JP3748703B2 (en) Trimming groove inspection method for chip resistors
JPH05283825A (en) Printed-circuit board with identification mark
KR101084931B1 (en) Printed circuit board with solder-resist shift coupon and the method of manufacturing the thereof, and method for testing substrate using the same
JPH02198186A (en) Method of inspecting printed circuit board shielding layer and inspecting means thereof
KR101101237B1 (en) The planarization process for the surface of multilayer ceramic substrate in probe card
JPH0621180A (en) Inspecting method for misregistration of solder-resist layer of printed wiring board
JPH03283544A (en) Method for continuity test of contact hole in semiconductor device
JPH0621623A (en) Method for processing solder resist in manufacture of printed wiring board
JPH05160544A (en) Manufacture of printed circuit board
JP2003021606A (en) Method for inspecting wiring board applied with transparent organic insulating film
JPH05160555A (en) Printed circuit board
JP2000307249A (en) Multilayer printed board
JPH05327153A (en) Wiring substrate and inspecting method thereof
JPH05160554A (en) Printed circuit board
JPH0537100A (en) Printed wiring board and checking of marking printing in printed wiring board