JPS607729A - Flattening method of selectively epitaxial grown layer - Google Patents

Flattening method of selectively epitaxial grown layer

Info

Publication number
JPS607729A
JPS607729A JP11750883A JP11750883A JPS607729A JP S607729 A JPS607729 A JP S607729A JP 11750883 A JP11750883 A JP 11750883A JP 11750883 A JP11750883 A JP 11750883A JP S607729 A JPS607729 A JP S607729A
Authority
JP
Japan
Prior art keywords
etching
epitaxial growth
insulating film
grown layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11750883A
Other languages
Japanese (ja)
Inventor
Hiromi Sakurai
桜井 弘美
Hirotomo Ooga
大賀 弘朝
Hirotsugu Harada
原田 「ひろ」嗣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11750883A priority Critical patent/JPS607729A/en
Publication of JPS607729A publication Critical patent/JPS607729A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to flatten a selectively epitaxial grown layer by a method wherein an etching method is used in which the etching speed is rather large when the incidence of an etching medium is inclined in relation to an etching surface. CONSTITUTION:An SiO2 film 2 is formed on the surface of an Si substrate 1. The desired openings are formed in succession, and epitaxial growth of Si is performed from the top surface thereof to form Si epitaxial grown layers 3a, 3b. At this time, protrusions 4 are generated at the peripheries of the opening parts, and moreover clusters 5 are formed on the film 2. Then high-frequency sputter etching is performed from the upper part of the layers 3a, 3b and the film 2. When high-frequency sputter etching is performed in such a way, the slanting surfaces are etched higher than the flat parts at first to remove the clusters 5 and the protrusions 4, etc. The etching speed at the horizontal is slow sgainst thereto. Accordingly, flattening of the selectively epitaxial growth layer can be attained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体集積回路装置の製造に当って用いられ
る選択エピタキシャル成長によって得られる半導体成長
層の表面の平坦化方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for planarizing the surface of a semiconductor growth layer obtained by selective epitaxial growth used in the manufacture of semiconductor integrated circuit devices.

〔従来技術〕[Prior art]

近年集積回路装置において高密度集積化、高性能化を図
る目的で新しい素子間分離方法が開発されている。中で
も選択エピタキシャル成長方法は低圧エピタキシャル成
長技術の導入により優れた結晶性のエピタキシャル成長
層が得られるようになってきており、従来の平坦な工く
タキシャル成長層の一部をエツチングおよび選択酸化す
る方法と比較して、バードビークによる横方向の食い込
みもなく、極めて集積度の高いデバイスを得ることがで
きる。しかしながら、この新しい技術においては絶縁膜
の開口面積や隣接する開口部の形状により突起の形状が
異ると云う問題があった。
In recent years, new element isolation methods have been developed for the purpose of achieving higher density integration and higher performance in integrated circuit devices. Among them, the selective epitaxial growth method has become possible to obtain an epitaxial growth layer with excellent crystallinity due to the introduction of low-pressure epitaxial growth technology, and compared to the conventional method of etching and selectively oxidizing a part of the flat taxial growth layer. Therefore, it is possible to obtain an extremely highly integrated device without lateral encroachment caused by bird's beak. However, this new technology has a problem in that the shape of the protrusion varies depending on the opening area of the insulating film and the shape of adjacent openings.

以下、シリコン(Sl)を半導体基板とする従来の選択
エピタキシャルの欠点について説明する。
Hereinafter, the drawbacks of conventional selective epitaxial method using silicon (Sl) as a semiconductor substrate will be explained.

第1図は選択エピタキシャル成長後の構造断面図であっ
て、図において、11)は81基板でその表面を酸化し
て酸化シリコン(S102)膜(2)を形成する。
FIG. 1 is a cross-sectional view of the structure after selective epitaxial growth, and in the figure, 11) is an 81 substrate whose surface is oxidized to form a silicon oxide (S102) film (2).

つづいて、所望の開口を設け、これらの上面から81の
エピタキシャル成長を行って81工ピタキシヤル成長層
(”a)+ (31))を形成する。
Subsequently, desired openings are provided and 81 epitaxial growth is performed from the upper surfaces of these openings to form an 81-hole epitaxial growth layer ("a)+ (31)).

この時ジクロルシラン(stu2cz2)の熱分解で絶
縁膜(2)上にはSlを成長させることなく、開口部内
のみSlを成長させることが理想的であるが、実際は開
口面積に依存して開口部周辺に突起(4)が生じ、しか
も、開口部の周辺の絶縁膜(2)上には単結晶でなく多
結晶を形成する。また、絶縁膜(2)上には小さなSl
のクラスター(5)が所々形成される。前者の突起物(
4)は開口面積により高さが種々異る。例えば、1μm
の厚さの絶縁膜(2)を用い1.2μmの厚さにエピタ
キシャル成長を行ったとき、突起(4)の高さは絶縁膜
(2)の表面から0.2−1.2μmの範囲で成長する
。クラスター(6)についても同様である。この高さの
違いにより、微細加工を行う際に形成する図示しない薄
いレジスト膜の一部にピンホールが生じたり、レジスト
膜と下地との密着性が惑くなったりして、デバイス製造
上極めて不都合な結果をまねく。つまり、ピンホールを
介しての不用のエツチングや、イオン注入等が生じたり
、エツチング時の突起部(4)の近傍におけるレジスト
膜のはがれによる異常エツチング等が生じる。
At this time, it is ideal to grow Sl only within the opening without growing it on the insulating film (2) by thermal decomposition of dichlorosilane (stu2cz2), but in reality, depending on the opening area, the area around the opening may grow. A protrusion (4) is formed on the opening, and polycrystalline instead of single crystal is formed on the insulating film (2) around the opening. Moreover, on the insulating film (2), a small Sl
Clusters (5) are formed in some places. The former protrusion (
4) has various heights depending on the opening area. For example, 1 μm
When epitaxial growth is performed to a thickness of 1.2 μm using an insulating film (2) with a thickness of grow up. The same applies to cluster (6). Due to this difference in height, pinholes may occur in a part of the thin resist film (not shown) that is formed during microfabrication, and the adhesion between the resist film and the underlying layer may be compromised, making it extremely difficult to manufacture devices. lead to unfavorable results. That is, unnecessary etching through pinholes, ion implantation, etc. may occur, and abnormal etching may occur due to peeling of the resist film near the protrusion (4) during etching.

更に、突起部(4)の上を通る配線は特に薄くなり、メ
タル配線のマイグレーションを急激に起しやすくなるこ
とも微細化を行うために問題となる。また、開口部周辺
に形成された多結晶S1にpn接合が形成された際、多
結晶中の拡散係数が単結晶の時の5〜lO倍であること
から高濃度側からの横方向拡散により、反対導電形の領
域に形成された電極の位置まで拡散されるので、みかけ
上の接合短絡を生じたり、多結晶で形成されたpn接合
のリーク電流が単結晶にくらべ大きいことによる過大な
接合リークを生じると云う問題があった。
Further, the wiring passing over the protrusion (4) becomes particularly thin, and migration of the metal wiring becomes more likely to occur rapidly, which is a problem due to miniaturization. Furthermore, when a pn junction is formed in the polycrystal S1 formed around the opening, the diffusion coefficient in the polycrystal is 5 to 1O times that of a single crystal, so lateral diffusion from the high concentration side , it is diffused to the position of the electrode formed in the region of the opposite conductivity type, causing an apparent junction short circuit, or an excessive junction due to the leakage current of a pn junction formed of polycrystal being larger than that of a single crystal. There was a problem with leaks.

〔発明の概狭〕[Narrowness of the invention]

この発明は以上のような点に鑑み−てなされたもので、
エツチング媒体の入射が被エツチング面に対して直角で
あるよりも斜めである場合の方がエツチング速度が大き
いようなエツチング方法を用いることによって選択エピ
タキシャル成長層表面を容易に平坦化できる方法を提供
するものである。
This invention was made in view of the above points.
To provide a method for easily flattening the surface of a selective epitaxial growth layer by using an etching method in which the etching rate is higher when the incidence of the etching medium is oblique than perpendicular to the surface to be etched. It is.

〔発明の実施例〕[Embodiments of the invention]

第2図はこの発明の一実施例を説明するための断面図で
、第2図Aに示すように、第1図にって説明した方法で
形成された選択エピタキシャル成長層(3a)、 (3
b)および絶縁膜(2)の上部からアルゴン(Ar)イ
オン(矢印工で示す。)により高周波(RF)スパッタ
エツチングを行うことで第2図Bに示すような形状が得
られる。RFスパッタエツチングの特徴はG、 K、 
Wehner 〔、r、 Appl、 phys、 2
5 (1954) 270〕により多結晶面では表面に
余1め方向からイオンが当たる方が、スノ(ツタエツチ
ング速度が速くなることが見い出されており、第3図B
に示すようにイオンの入射方向と被入射体(6)の被入
射面とのなす角をθとしたとへ、入射角θとエツチング
速度との間には第キ図Aに示すような従って、第2図÷
のようにアルゴンイオンを用いてスパッタエツチングを
行うと先ず斜めの面が平坦部よシ速くエツチングされて
しまい、クラスタ(5)や突起(4)等が無くなってし
まう。これに対して水平面はエツチング速度が遅い。我
々が実際に試みた条件を以下写真を用いて説明する0第
4図は選択エピタキシャル成長層形成直後の断面走査電
子顕微鏡(EIBM)写真である。酸化膜の膜厚は1.
6μmである。開口は酸化膜のドライエツチングを用い
ることで異方性エツチングされ垂直なエツジとなってい
る。選択エピタキシタル成長は低圧下で行い3.6μm
の厚さに形成した。
FIG. 2 is a cross-sectional view for explaining one embodiment of the present invention. As shown in FIG. 2A, selective epitaxial growth layers (3a), (3
b) and radio frequency (RF) sputter etching from the top of the insulating film (2) using argon (Ar) ions (indicated by arrows) to obtain the shape shown in FIG. 2B. The characteristics of RF sputter etching are G, K,
Wehner [, r, Appl, phys, 2
5 (1954) 270], it was found that on polycrystalline surfaces, when ions hit the surface from the opposite direction, the etching rate was faster, as shown in Figure 3B.
As shown in Figure A, if the angle between the incident direction of the ions and the incident surface of the target object (6) is θ, then there is a relationship between the incident angle θ and the etching rate as shown in Figure A. , Figure 2 ÷
When sputter etching is performed using argon ions as shown in the figure, the oblique surfaces are first etched faster than the flat areas, and clusters (5) and protrusions (4) are eliminated. On the other hand, the etching speed on the horizontal plane is slow. The conditions that we actually tried are explained below using photographs. FIG. 4 is a cross-sectional scanning electron microscope (EIBM) photograph immediately after the formation of a selective epitaxial growth layer. The thickness of the oxide film is 1.
It is 6 μm. The openings are anisotropically etched using dry etching of the oxide film to form vertical edges. Selective epitaxial growth was performed under low pressure to a thickness of 3.6 μm.
It was formed to a thickness of .

次に真空度が2XIOTorrの高真空中にサンプルを
入れ、lom TOrrのArガス中でIW/Cm2で
RFスパッタエツチングを行った。スパッタエツチング
をRFで行ったのは、絶縁膜があるため直流(DC)で
はスパッタエツチング速度が低いからである。3時間の
エツチング後の断面が第5図に示すSEM写真の通りで
ある。今回は充分厚いエピタキシャル成長を例にとった
ため、エピタキシャル成長層が絶縁膜よりも厚くなって
いるが、最初のエピタキシャル成長層厚を絶縁膜と同程
度に形成すると、第2図Bのように平坦になる。この方
法によると台形の81が残り、しかも酸化膜との境界も
スムーズであることがわかるであろう。台形の形状に対
する配線は極めて容易であって断線の問題は解決できた
。しかも、ポリシリコン部が全く無くなったために、ポ
リシリコンによる前述の問題も解決できた。平坦部での
このときのエツチングレートはSlに対し0.08 μ
m/h r 、 S io 2に対し0.18μm/h
rで5in2の方が速い。しかし、Siの斜め方向のエ
ツチング速度は0.5μm/hrでl)斜め方向は著し
く速くエツチングされる。
Next, the sample was placed in a high vacuum with a degree of vacuum of 2XIO Torr, and RF sputter etching was performed using IW/Cm2 in Ar gas at lom TOrr. The sputter etching was performed using RF because the sputter etching rate is low with direct current (DC) due to the presence of the insulating film. The cross section after etching for 3 hours is shown in the SEM photograph shown in FIG. This time, we have taken sufficiently thick epitaxial growth as an example, so the epitaxial growth layer is thicker than the insulating film, but if the initial epitaxial growth layer is formed to the same thickness as the insulating film, it will become flat as shown in Figure 2B. It will be seen that this method leaves a trapezoidal shape 81 and the boundary with the oxide film is smooth. Wiring for the trapezoidal shape was extremely easy and the problem of disconnection could be solved. Moreover, since there is no polysilicon part at all, the aforementioned problems caused by polysilicon can be solved. The etching rate at this time in the flat area is 0.08 μ for Sl.
m/hr, 0.18 μm/h for S io 2
5in2 is faster in r. However, the etching rate of Si in the diagonal direction is 0.5 μm/hr, and the etching rate in the diagonal direction is extremely high.

なお、上記実施例はArを用いて行ったがネオン(Ne
)lキセノン(Xe)、クリプトン(Kr)等の不活性
ガスを用いることでも同様の結果が得られる。また、絶
縁膜の厚さを選択エピタキシャル成長層の厚さより厚く
する方法も完全平坦化を行うことで充分可能である。更
に、RFスパッタエツチングに代る他の方法としてイオ
ンビームエツチング等の導入も可能である。
Note that although the above example was carried out using Ar, neon (Ne
) Similar results can be obtained by using an inert gas such as xenon (Xe) or krypton (Kr). Furthermore, a method of making the thickness of the insulating film thicker than the thickness of the selectively epitaxially grown layer is also possible by performing complete planarization. Furthermore, it is also possible to introduce other methods such as ion beam etching in place of RF sputter etching.

〔発明の効果〕〔Effect of the invention〕

以上説明したーようにこの発明ではエツチング媒体の入
射が被エツチング面に対して直角であるよりも斜めであ
る場合の方がエツチング速度が大きいようなエツチング
方法を用いることによって、選択エピタキシャル成長層
の平坦化が可能となり、選択エピタキシャル成長法の実
用化が可能となった0
As explained above, the present invention uses an etching method in which the etching rate is higher when the incidence of the etching medium is oblique to the surface to be etched than when it is perpendicular to the surface to be etched. 0, making it possible to put selective epitaxial growth into practical use.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は選択エピタキシャル成像後の状態を示す断面図
、第2図はこの発明の一実施例を説明するための断面図
、第3図はこの発明に用いるエツチング法のエツチング
速度の入射角依存性の一例を示す図、第4図は選択エピ
タキシャル層形成直後の断面8118M写真、第5図は
この発明による平坦化を施した後の断面EIEM写真で
ある。 図において、(1)は半導体基板、(2)は絶縁膜、(
3a)、 (31))は選択エピタキシャル成長層、(
4)Gl半導体突起、(6)は島(クラスター)である
。 なお、図中同一符号は同一または相当台す分を示す。 代理人 大岩増雄 第1 t4 第2図 第33[′ス1
Fig. 1 is a cross-sectional view showing the state after selective epitaxial image formation, Fig. 2 is a cross-sectional view for explaining an embodiment of the present invention, and Fig. 3 is the dependence of the etching rate on the incident angle of the etching method used in the present invention. FIG. 4 is a cross-sectional 8118M photograph immediately after forming a selective epitaxial layer, and FIG. 5 is an EIEM photograph of a cross-section after planarization according to the present invention. In the figure, (1) is a semiconductor substrate, (2) is an insulating film, (
3a), (31)) are selective epitaxial growth layers, (
4) Gl semiconductor protrusion, (6) is an island (cluster). Note that the same reference numerals in the figures indicate the same or equivalent units. Agent Masuo Oiwa 1st t4 Figure 2 33['s1

Claims (1)

【特許請求の範囲】 +11 半導体基板の一生面上に絶縁膜を形成し、この
絶縁膜の一部に開口部を設け、この開口部に露出した上
記半導体基板の表面上に半導体層を選択的にエピタキシ
ャル成長させたときに尚該選択エピタキシャル成長層の
周辺部に生じる半導体突起および多結晶半導体層並びに
上記絶縁膜上に生じる多結晶半導体からなる島を除去す
るに際して、上記主面側上面全面にわたってエツチング
媒体の入射が被エツチング面に直角であるよりも斜めで
ある場合の方がエツチング速度が大きいような異方性エ
ツチングを施すことを特徴とする選択エピタキシャル成
長層の平坦化方法。 (2) エツチングに高周波スパッタエツチングを用い
ることを特徴とする特許請求の範囲第1項記載の選択エ
ピタキシャル成長層の平坦化方法。 (3) エツチングにイオンビームエツチングを用いる
ことを特徴とする特許請求の範囲第1項記載の選択エピ
タキシャル成長層の平坦化方法。
[Claims] +11 An insulating film is formed on the entire surface of a semiconductor substrate, an opening is provided in a part of the insulating film, and a semiconductor layer is selectively formed on the surface of the semiconductor substrate exposed to the opening. When removing the semiconductor protrusions and polycrystalline semiconductor layers that are generated at the periphery of the selective epitaxially grown layer and the islands of polycrystalline semiconductor that are generated on the insulating film when epitaxially grown, an etching medium is applied over the entire top surface on the main surface side. A method for planarizing a selectively epitaxially grown layer, the method comprising performing anisotropic etching such that the etching rate is higher when the incidence of the etching surface is oblique than perpendicular to the surface to be etched. (2) A method for planarizing a selective epitaxially grown layer according to claim 1, characterized in that high frequency sputter etching is used for etching. (3) A method for planarizing a selective epitaxial growth layer according to claim 1, characterized in that ion beam etching is used for etching.
JP11750883A 1983-06-27 1983-06-27 Flattening method of selectively epitaxial grown layer Pending JPS607729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11750883A JPS607729A (en) 1983-06-27 1983-06-27 Flattening method of selectively epitaxial grown layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11750883A JPS607729A (en) 1983-06-27 1983-06-27 Flattening method of selectively epitaxial grown layer

Publications (1)

Publication Number Publication Date
JPS607729A true JPS607729A (en) 1985-01-16

Family

ID=14713490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11750883A Pending JPS607729A (en) 1983-06-27 1983-06-27 Flattening method of selectively epitaxial grown layer

Country Status (1)

Country Link
JP (1) JPS607729A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381029A (en) * 1991-03-01 1995-01-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including semiconductor layer having impurity region and method of manufacturing the same
JP2008035717A (en) * 2006-08-01 2008-02-21 Iseki & Co Ltd Combine

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381029A (en) * 1991-03-01 1995-01-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including semiconductor layer having impurity region and method of manufacturing the same
US5446301A (en) * 1991-03-01 1995-08-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including semiconductor layer having impurity region and method of manufacturing the same
JP2008035717A (en) * 2006-08-01 2008-02-21 Iseki & Co Ltd Combine

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