JPS6076826A - Echo canceller - Google Patents

Abstract

PURPOSE:To decrease the number of input/output terminals by dividing the output value of an accumulation circuit of each transversal filter into small parallel data. CONSTITUTION:An accumulation circuit 9 contains accumulators 12 and 13 of each L/2 bits to constitute an L bits totalizer. The carry signal of the accumulator 12 is added to the least significant bit of the accumulator 13. The output values of accumulators 12 and 13 are successively outputted in a time division mode and selectively by a time division switch circuit 11. The output signal of the circuit 11 has L/2 bits. A selection circuit 10 outputs selectively the L-bit output of a multiplier 8 to multipliers 12 and 13 during a convolutional operation, then outputs selectively the fixed value ''0'' and the output of circuit 11 of transversal filter of the preceding stage after the convolutional operation is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an echo canceling device, and more particularly to a structure for reducing the number of input/output terminals at each step of an echo canceling device in which a plurality of transversal filters are connected in cascade.

Conventionally used echo suppression devices perform switching control that compares the transmitting and receiving signals and turns on the line with the higher level, and turns off or attenuates the line with the lower level. disconnection.

There are drawbacks such as generation of click noise. In recent years, echo cancelers have been developed to eliminate this drawback. This is achieved by providing a pseudo echo path that simulates the characteristics of the echo path, and
The echo signal is eliminated by synthesizing a pseudo echo signal from the signal and subtracting the pseudo echo signal from the echo signal generated from the actual echo path. The pseudo-echo path is mainly composed of transversal filters, and the pseudo-echo signal is
The tap coefficients of the transversal filter and the reception signal No. 4 are combined by a convolution operation. In recent years, in order to downsize devices and reduce power consumption, there has been a trend toward LSI-based echo cancellation devices, and the above-mentioned transversal filters have come to be configured as +te by cascading a plurality of transversal filters. However, when transversal filters are connected in cascade, a large number of parallel input/output terminals are required in order to add the results of convolution operations that are the outputs of the respective transversal filters, which has the disadvantage of increasing the number of terminals.

FIG. 1 is a block diagram showing an example of a conventional echo canceling device.
0 and 200 are connected in cascade to form a transversal filter with 2N taps. Receiving side input terminal 1
The received No. 4 X manually inputted from the receiving side output terminal 2 is sent to a receiving terminal (not shown), and is also input to the received No. 4 storage circuit 7 of the transversal filter 100.

The received signal storage circuit 7 stores input values for each time slot for N time slots. Then, the multiplication circuit 8 multiplies the N-step tap coefficients of the tap coefficient storage circuit 6 by the input signal of each step of the received signal storage circuit 7, and the result is accumulated in the accumulation circuit 9. That is, a convolution operation is performed. Within one time slot, the above-mentioned N multiplications and the accumulation of the multiplication results are performed. On the other hand, the received signal storage circuit 7' of the transversal filter 200 stores the received signal No. 4 N time slots earlier than the received signal No. 4 of the received signal storage circuit 7, and the received signal No. 4 of the received signal storage circuit 7' is stored. It is multiplied by the content and accumulated in the accumulation circuit 9'. The convolution operations in both transversal filters are performed in parallel, and the accumulated results are input at the same time. After the convolution processing, the L-bit output of the accumulator 9 is sent in parallel to the accumulator 9', and the accumulator 9' stores the sum of the output values of both transversal filters.
That is, an output value as a transversal filter with a tap coefficient of 2N can be obtained. This output value is a pseudo echo signal Y, and the subtracter 5 takes the difference from the transmitting No. 4 Y (when there is a lot of transmission, it is an echo signal), and the residual echo signal e is output from the transmitting side output terminal 4. It will be sent out as soon as possible. The above poem;
The outputs of the arithmetic circuits 9 and 9' are parallel outputs of L bits, so if all L input/output terminals are connected in cascade to 3 and transversal filters, 2L- input/output terminals are obtained. As a result, the number of input/output C'HA children increases as described above. The contents of the prefecture 9 circuits g and g'J may be added by separate adders and then supplied to the subtracter 5, but the reason for increasing the number of terminals is the same as described above.

The purpose of the present invention is to alleviate the above-mentioned conventional drawbacks and to reduce the human output ψ
An object of the present invention is to provide an echo canceling device that can be constructed by cascading transversal filters with a reduced number of filters by 911.

The erasing device of the present invention includes a received signal storage circuit, a tap coefficient storage circuit, a multiplication p(path) for multiplying the content of the received signal storage circuit and the content of the tap coefficient storage circuit, and A plurality of transversal filters each comprising an accumulation circuit for accumulating outputs are provided, and the plurality of transversal filters are connected in cascade to calculate the sum of the output values of the accumulation circuits of the respective transversal filters. Sending β
In the echo canceling device that cancels the echo signal by subtracting the echo signal from each signal, each of the transversal filters divides the output data of the accumulator circuit into a plurality of sets of small parallel data. The present invention is characterized in that the total sum of all accumulation circuit outputs is calculated by adding or accumulating the outputs of the time division switch circuits that sequentially time divisionally output small parallel data.

In addition, a selection circuit is provided to input the output of the multiplier circuit to the accumulator circuit during the daytime operation, and after the convolution operation is completed, the output of the time division switch circuit of the previous stage filter is input to the accumulator circuit. If you input it sequentially into the digit input field,
There is no need to provide a separate adder to add the outputs of each filter.

Next, "misfire" will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing the input/output configuration of an accumulator circuit in 1r i'iji, which is one embodiment of the present invention. In this embodiment, the conventional echo canceling device shown in FIG.
The input/output circuit shown in FIG. 2 is used for the input/output of the circuit 90, and the other parts are as shown in FIG.
1. The accumulator circuit 9 has two L72-bit accumulators 12 and 13 (+iii) and the total L-bit accumulator is horizontal. T position L
It's an accumulator that accumulates all 72 pints.

The accumulator 13 accumulates the upper L/2 pi)k. Accumulator 12
The carry sacrum is of course added to the least significant bit of accumulator 13. The output values of the accumulators 12 and 13 are sequentially and selectively output by the time division switch circuit 11 in a time division manner. The output signal of the time division switch circuit 11 is L/2 bits. The selection circuit 10 inputs the output value (L bit) of the multiplier 8, the output (L/2 bit) of the time division switch circuit 11 of the transversal filter in the previous stage, and the fixed value "0" of the L/2 bit. During the convolution operation, the L pinto output of the multiplier 8 is selectively output, and L/2 bits are input to the corresponding digit inputs of the accumulators 12 and 13, respectively.

After the convolution operation is completed, the output (L/2 bits) of the time division switch circuit 11 of the transversal filter in the previous stage is
and select the fixed value "0"' (L/2 bit),
First, the value of the lower L/2 bits sent from the previous stage is input to the accumulator 12, and the fixed value 1101+ is input to the accumulator 13.
Next, the upper L/2 bit value sent from the previous stage is input to the accumulator 13, and the fixed value "θ'' is input to the accumulator 12.

Therefore, accumulators 12, 13 are used as multipliers 8 during convolution operations.
After the convolution operation is completed, the lower L/L of the previous accumulation result is sent to the accumulator 12.
Two bits are added, and then the upper L/2 bits from the previous stage are added to the accumulator 13. In other words, the cumulative result is 11
The result of adding the outputs of the first-stage transversal filter is input. The selection circuit 10 described above is ineffective in the first stage transversal filter. Further, the cumulative results of the transversal filter of the j1 evening range are outputted from the time division switch circuit 11 in J7/2 bits each and subtracted from the anti-Xibogo Y by the first subtractor 5. In this embodiment, the signal output from the time division switch circuit 11 to the next stage is L72 bits, so the number of input/output terminals is j, J, /2. That is, compared to the conventional configuration, the number of human output terminals can be reduced by half. Of course, the number of input/output terminals can be further reduced by dividing the accumulator into even more parts. In this embodiment, the output of the time division switch circuit 11 is inputted to the selection circuit 10 of the fourth-stage transversal filter.
The two outputs may be added by a single adder (not shown).

-θ) "Koha is Oichi Q Old 1st Road 10 is no V, non-deho-
Therefore, an additional adder is required.

As described above, in the present invention, the output ([1f] of the cumulative nine circuits of each transversal filter is divided into multiple sets of small parallel data, and each small parallel data is output in a time-sharing manner. Therefore, it has the effect of reducing the number of input 11:I input terminals.A short selection circuit is provided to accumulate the multiplier output during the convolution operation, and after the convolution operation is completed, it is possible to reduce the number of input terminals. If the configuration is configured such that the output value of the previous stage inputted from the filter in a time-sharing manner is added to the cumulative result, the output value of each stage filter is combined without providing a separate adder, and a pseudo+L;I, scale signal is obtained. It is possible to create
Since the number of bits of the output 111 of each filter is reduced by +41, it has the effect of reducing the number of input and output terminals of each stage filter. In other words, cascade connections can be easily made with a small number of terminals, making it possible to downsize the device and reduce power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional echo canceling device e(-), and FIG. 2 is a block diagram showing an example of an input/output configuration of an accumulation path in an embodiment of the present invention. In, 1... Receiving side input terminal, 2... Receiving side output terminal, 3... Sending side input terminal, 4... Sending side output terminal, 5... Reduction: MA device, 6, 6 '...Tap coefficient storage circuit, 7.7'...Reception No. 16 storage circuit, 8...
・Eisan circuit, 9゜9'・Accumulator circuit, 1j...Time division switch circuit, 10...Selection circuit, 1.2, 1.3・
... Accumulator, 100, 200... Transversal filter, X... Received signal, Y... Echo signal, Y...
- Pseudo echo signal, e...Residual echo signal. Representative Patent Attorney Sumi 1) Sou Toshi

Claims (2)

[Claims] (1) A received signal storage circuit, a tap coefficient storage circuit, a multiplication circuit that multiplies the contents of the received signal storage circuit and the tap coefficient storage circuit, and an accumulator that accumulates the output of the multiplication circuit. the plurality of transversal filters are connected in cascade, and the sum of the output values of the accumulation circuits of the respective transversal filters is subtracted from the transmission No. 4; In the echo canceling device for canceling the echo signal using 1. An echo canceling device comprising: a time division switch circuit that sequentially performs time division output; and calculating the sum of all accumulator circuit outputs by adding or accumulating the outputs of the time division switch circuit. (2) In the echo canceling device according to claim 1, inputting the output value of the multiplication circuit, the output value of the time division switch circuit of the preceding stage transversal filter, and a fixed value "0", During the convolution operation, the output of the multiplication circuit is input to the accumulation circuit, and after the convolution operation is completed,
It is characterized by comprising a selection circuit that sequentially inputs the small parallel data output from the time division switch circuit in the previous stage to the bit input of the corresponding digit of the accumulator circuit, and inputs "0" to the input of other digits. What to do.