JPH06181425A - Digital filter - Google Patents

Abstract

PURPOSE:To realize the digital filter with fast filtering processing as a whole by providing a coefficient updating sequencer comprising an adder storing sequen tially the sum of coefficients outputted sequentially to a 2nd coefficient storage means. CONSTITUTION:An output signal Y(n) read from an output storage register and a reference value a(n) read from a reference value storage register are subtracted by a subtractor in an arithmetic operation section. Then a 1st numeral alpha is multiplied with a value d(n)-Y(n) after the substraction by the first multiplier to produce a product alpha.(d(n)-y(n)) and it is inputted to an adder. Furthermore, a filter coefficient c(n) read from a coefficient storage register is inputted to the adder. A logic circuit with very simpler configuration than that of a processor is provided in this way and the arithmetic operation of the ZF method is executed in a very short time such as one clock time for the arithmetic operation of one filter coefficient.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to FIR (Finite).
The present invention relates to an Impulse Response (Digital) type digital filter, and more particularly to a digital filter used in a so-called adaptive filter system that automatically determines a filter coefficient based on input data and obtains a desired filter characteristic using this filter coefficient.

[0002]

2. Description of the Related Art In recent years, digital filters have been used in the above adaptive filter systems. Ghost phenomenon caused by reflected radio waves from skyscrapers in television broadcasting (a phenomenon in which images are overlapped with double or triple shifts)
Examples thereof include a ghost canceller that removes noise and an echo canceller that eliminates an echo phenomenon in a telephone or the like.

In such an adaptive filter system, a reference signal of a predetermined standard is periodically transmitted,
The transmitted reference signal is received by the receiving side and input to the digital filter, the output signal of the digital filter is compared with the reference signal stored in advance, and the digital filter is used to reduce the difference between these signals. The noise is mixed in the signal (the image signal in the case of a ghost canceller and the audio signal in the case of an echo canceller) by a digital filter whose filter coefficient is sequentially updated in this way. ) Is removed.

FIG. 3 is a circuit block diagram showing the configuration of the FIR type digital filter. Input signal sequence ..., u
(N−m), u (n−m−1), ..., u (n−3), u
(N-2), u (n-1), u (n), ... Are sequentially input to the leading tap of the plurality of taps forming the shift register in time series, and are synchronized with a clock (not shown). Sequentially to the previous tap. The respective input signals input to the plurality of taps are ... u (n-m), u (n-)
m-1), ..., u (n-3), u (n-2), u (n-
1), u (n), ... Are input to each multiplier provided corresponding to each tap. Further, each coefficient register is provided corresponding to each tap, and each coefficient w (0), w (1), ..., W (m) is set in each coefficient register, and each coefficient w ( 0), w (1), ..., W (m) are input to the corresponding multipliers. In each multiplier, the respective input signals input, u (n-m), u (n-m-1),
..., u (n-3), u (n-2), u (n-1), u
(N), ... Each coefficient w (0), w (1), ..., W (m)
Are multiplied by each other and then added together by an adder to obtain an output signal y (n)

[0005]

[Equation 1]

Is output. The output signal indicated by (1) is the input signal where each coefficient w (0), w (1), ...,
Predetermined filtering such as high-pass filtering or low-pass filtering is performed according to the value of w (m). FIG. 4 shows a conventional example in which this FIR filter is configured as an adaptive filter system.

In addition to the FIR filter, this system is provided with a memory for storing an output signal, a reference signal storage memory for storing a reference signal sequence, and a processor for calculation. A reference signal that is periodically transmitted and received via a predetermined transmission path (for example, a transmission path by radio waves between a television station and a television receiver) is input as an input signal to the FIR filter, and the FIR filter at that time is input. The output signal (see the equation (1) above) is stored in the memory. After that, the output signal stored in the memory is sequentially read out, the reference signal stored in the reference signal storage memory is also sequentially read out, and the read output signal and the reference signal are compared by the processor, A new filter coefficient that reduces the difference between the two is generated, and the new filter coefficient is stored in the coefficient register shown in FIG.

Various methods are known as a method for generating a filter coefficient, and one of them is ZF.
There is a method called (Zero Forcing method). In this ZF method, the output signal sequence of the digital filter is y (n), the reference signal sequence stored in the reference signal storage memory is d (n), and the filter before update stored in the coefficient register (see FIG. 3). When the coefficient is c (n) and the updated filter coefficient is c ′ (n), c ′ (n) = c (n) + α · (d (n) −y (n)) (2) , Α is a predetermined constant. According to the equation (2), the processor shown in FIG. 4 performs the calculation.

[0009]

In the adaptive filter system as shown in FIG. 4, as shown in equation (2),
Difference d (n) between the reference signal example d (n) and the output signal y (n)
If the calculation is performed based on -y (n) and the signal sequences of both are long, the calculation time required for comparison in the processor cannot be ignored, and the processing speed of the system decreases by the amount of this comparison processing calculation. There is a problem that it ends up.

In view of the above-mentioned circumstances, it is an object of the present invention to provide a digital filter with an improved processing speed.

[0011]

The digital filter of the present invention for achieving the above object is composed of the following FIR filter and coefficient updating sequencer. The FIR filter that constitutes the present invention includes (1) a plurality of registers that output serially input digital time series data in synchronization with a clock signal (2) to weight the data output from each of the plurality of registers (3) Multiplying the data output from the plurality of registers by each coefficient output from the coefficient storing means corresponding to each register and adding them to each other across the plurality of registers. The sum-of-products calculation means sequentially generates output data according to.

Further, the coefficient update sequencer constituting the present invention is (4) a plurality of reference value storage means for storing each predetermined reference value, and (5) a plurality of coefficient storage means (above (2)). A plurality of second coefficient storage means for storing each coefficient (6) Difference calculator for sequentially calculating the difference between the output data sequentially output from the FIR filter and the reference value sequentially output from the reference value storage means ( 7) A first multiplier that multiplies the output of the difference calculator by a predetermined first numerical value. (8) The output of the first multiplier and the coefficients sequentially output from the second coefficient storage means are added and added. The result is stored in an adder for sequentially storing the result in the second coefficient storage means.

[0013]

The digital filter of the present invention has the above-mentioned (1) to (1).
In addition to the FIR filter of (3), the above (4) to (8)
Since the coefficient update sequencer is provided, the coefficient update sequencer can generate one filter coefficient in, for example, one clock, which speeds up the filter coefficient generation operation, and therefore the processing speed of the digital filter. Is improved. Further, the coefficient updating sequencer has a simple structure and requires a small-scale circuit. Therefore, it becomes a digital filter which is small and low-cost as a whole as compared with the case where a complicated processor having a conventional structure is provided.

[0014]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a block diagram showing an example of configuring an adaptive filter system using a digital filter according to an embodiment of the present invention. This filter system is composed of an FIR type filter having the same configuration as that shown in FIG. 3, a reference signal storage memory, and a coefficient update sequencer / buffer. Compared with the conventional system shown in FIG. 4, the memory for storing the output signal is not necessary and has been removed. Instead of a processor having an extremely complicated configuration, the coefficient of a simple configuration as shown below is used. An update sequencer / buffer is provided.

FIG. 2 is a circuit block diagram showing a configuration of the coefficient update sequencer / buffer shown by a block in FIG. This coefficient update sequencer / buffer is composed of a register section and an arithmetic section. The register section has a plurality of output storage registers for sequentially storing the output signal y (n) of the FIR filter shown in FIG. The reference value storage register for storing the reference value α (n) read from the reference signal storage memory shown in and the coefficient storage register for storing the filter coefficient c (n) are provided. The output signal y (n), the reference value d (n), and the filter coefficient c (n) stored in these registers are sequentially read out in synchronization with a clock (not shown) and input to the arithmetic unit.

In the arithmetic unit, the output signal y (n) read from the output storage register and the reference value α (n) read from the reference value storage register are subtracted by the subtractor to obtain the first multiplier. The subtracted value d (n) -y (n) is multiplied by a predetermined first numerical value α to obtain a value α · (d (n) -y
(N)) is generated and input to the adder. The filter coefficient c (n) read from the coefficient storage register is also input to the adder. In the adder, the two input values α
(D (n) -y (n)) and c (n) are added to each other,
A new filter coefficient c ′ (n) is output (see equation (2)). This new filter coefficient c '(n) is stored in the coefficient storage register. The above calculation is repeatedly performed in synchronization with the clock signal, whereby a new set of filter coefficients c ′ (n) (n = 0, 1, ..., M) is stored in the coefficient storage register. A new set of filter coefficients c '(n) (n = 0,
1, ..., M) are transferred to the coefficient register of the FIR filter shown in FIG.

As described above, the above embodiment is provided with a logic circuit having an extremely simple structure as compared with the conventional processor, and by this logic circuit, the ZF method operation is performed in an extremely short time for calculating one filter coefficient, for example, one clock. Is performed. Further, this logic circuit is smaller in size and lower in cost than the conventional processor, and contributes to downsizing and cost reduction of the entire digital filter.

Although the above embodiment is provided with the output storage register for temporarily storing the output signal y (n) of the FIR filter (FIG. 3), this is not always necessary. For example, since the timing at which the reference signal is received and input to the FIR filter is known in advance, the reference value and the filter coefficient are stored in the reference value storage register and the coefficient storage register, respectively, prior to that timing, and the reception is performed. The reference value storage register and the reference value d (n) and the filter coefficient c (n) may be read from the reference value storage register and the coefficient storage register at the timing when the reference signal is output as the output signal (n) from the FIR filter, and may be input to the calculation unit. . In this case, the output storage filter is unnecessary.

[0019]

As described above, since the digital filter of the present invention is the conventional FIR filter provided with the coefficient updating sequencer of the above-mentioned simple structure, the ZF
The calculation for updating the filter coefficient using the method is completed in an extremely short time, and a digital filter having a high filtering processing speed can be realized as a whole. Further, since the coefficient updating sequencer has a simple structure, it contributes to downsizing and cost reduction of the digital filter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example in which an adaptive filter system is configured using a digital filter according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of a coefficient update sequencer / buffer shown as a block in FIG.

FIG. 3 is a circuit block diagram showing a configuration of a FIR type digital filter.

FIG. 4 shows a conventional example when configured as an FIR filter type adaptive filter system.

Claims (1)

[Claims] 1. A plurality of registers that output digital time-series data that are serially input in synchronization with a clock signal, and a plurality of registers that store respective coefficients for weighting the data output from each of the plurality of registers. Output data by multiplying each data output from the coefficient storage means and the plurality of registers by each coefficient output from the coefficient storage means corresponding to each register and adding the multiplied values to each other across the plurality of registers. An FIR filter composed of product-sum calculation means that are sequentially generated, a plurality of reference value storage means for storing respective predetermined reference values, and a plurality of second coefficient storage means for storing respective coefficients stored in the plurality of coefficient storage means. Before the output data sequentially output from the coefficient storage means and the FIR filter and the sequential output from the reference value storage means Difference computing unit which sequentially calculates the difference between the reference value, the output of said difference calculator with a predetermined 1
A first multiplier for multiplying the numerical value of, and an output of the first multiplier and the coefficient sequentially output from the second coefficient storing means are added, and a result of the addition is stored in the second coefficient. A digital filter comprising a coefficient update sequencer including an adder for sequentially storing in the means.