JPS5955618A - Transversal filter - Google Patents

Abstract

PURPOSE:To simplify the constitution of a filter with long top length and a filter with high sampling frequency by cascade-connecting units each of which has a memory and a multiplier. CONSTITUTION:A transversal filter is obtained by cascade-connecting tap slice units. The 2nd output terminal 101 of the prestage is connected to the 1st input terminal 100 of the poststage. The sum of signals outputted from the 1st output terminal 103 is used as a filter output. A signal inputted to the terminal 100 is written in a data memory 102 through a selector 16. An operator 12 finds out a factor correcting value from an output signal of the data memory 10 and a residual signal of the data memory 10 and a residual signal inputted to an input terminal 102. The unit multiplies a value obtained by correcting data from a factor memory 11 by the output of the data memory 11 and outputs the multiplied value from the terminal 103. Consequently, an accumulator is unnecessary in each unit.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to the quality of transversal filters.

[Technical background of the invention]

A transversal filter is one of the important technologies in the field of communication, and consists of a delay memory with taps at intervals of T seconds, and its output signal yk at time t=KT, the input signal Xk, and the tap coefficient hn. Sum of products Yk=Σh, X1. -1. N is the number of taps (
1) Obtained by n=1. In particular, transversal filters with variable tap coefficients are called adaptive filters and are used in echo cancellers, automatic equalizers, and the like. For example, an echo canceller is used for bidirectional communication between two-wire and four-wire lines, and removes echo components caused by mismatching of hybrid coils provided at conversion points of both lines. The adaptive transversal filter obtains the estimated value of the impulse response of this echo path, and the required number of taps N is the time tL for the impulse response to rise.
It depends on the sampling frequency fS (=H) of the input signal. For example, tr, = 32m5 + fs = 8
．． If TG (z), then N times 256 or more.As shown in equation (1), this is the amount of calculations for multiplication and addition required in the transversal filter.In the echo canceller, the equation In addition to (1), it is necessary to perform correction calculations for the tap coefficients with the same amount of calculations as in equation (1).

As described above, the high speed of the multiplier is a key point in the practical application of transversal filters with long tap lengths such as echo cancellers.

From the point of view of high speed, a parallel multiplier is of course suitable, but it increases the circuit scale and complexity due to wiring etc.1. Serial multipliers are suitable in terms of size and power consumption, but with the processing speed of current devices,
It is extremely difficult to perform all the necessary multiplications with one multiplier, and multiple multipliers are required. On the other hand, when implementing transversal filters with long tap lengths, especially in digital LSI implementation, the problem is the memory size for storing input signals and tap coefficients. t′ divided into LSI
One is preferable. The above problems are not limited to echo cancellers, but apply to all transversal filters depending on the required sampling frequency and tap length.

[Problems with background technology]

Transversal filters with long tap lengths and transversal filters with high sampling frequencies are constructed using multiple pieces of hardware (hereinafter referred to as tap slice units) by dividing the taps, especially when implemented in digital LSI. I hope so. FIGS. 1 and 2 are examples in which a conventional tap slice unit is applied to an echo canceller. The 4-wire side received signal (transmitted signal from the far end terminal) passes through terminals 1 and 2 and the hybrid coil 5,
It is received by the near-end terminal 6 on the 2-line side. The transmission signal of the near-end terminal 6 is sent to the hybrid coil 5. It is transmitted via terminals 3 and 4 to the far end terminal. A part of the received signal on the 4-wire side leaks to the transmitting side due to mismatching of the hybrid coil 5 and becomes an echo. What cancels this echo is an echo canceller composed of tap slice units 71 and 72.7M, an adder 8 and a subtracter 9. The second stage unit 7 includes a data memory IJIO, a coefficient memory 11. Coefficient correction amount calculator 12, adder 131, multiplier 14. It is composed of an accumulator 15 and a selector 16.

The operations in FIGS. 1 and 2 are as follows. The first input terminal 100 is connected to the first output terminal of the previous unit, and the selector 16 selects the input signal Xp (p=
k (= 1) N ) or the output signal x, -1 of the data memory 10 is selected and supplied to the data memory 10.

The first input terminal of the first stage unit receives the received signal X of terminal 1.
i is input. The contents of the data memory 10 are sequentially shifted through the memory to the first output terminal 101 . Arithmetic unit 129
The signal is supplied to a multiplier 14 and a selector 16. terminal 10
1 is connected to the first input terminal of the subsequent unit. The arithmetic unit 12 calculates a coefficient correction amount Δh1+ from the output signal X, -1 of the data memory 10 and the residual error i-k input from the second input terminal 102.

(g=(=-1)N) Δh1i+. =c[ekx, -0, n=1.2. -,
N1α: constant Calculates (2) and supplies it to the adder 13. The contents of the coefficient memory 11 are sequentially shifted through the memory and output signal hg+. is supplied to the adder 13. The adder 13 calculates the corrected tap coefficient hg+a hg+wa=hg+. +Δhg+n, ”='+ 2+
The multiplier 14 and the accumulator 15 supply ``'t N(3) to the calculation t/% multiplier 14 and the coefficient memory 11.
The output signal xp-ゎ of the data memory 10 and the output hg+n of the adder 13 are summed, and a partial sum yb is supplied to the second output terminal 103.

The partial sum yL of each unit) 71, 7□, 7M is summed by the adder 8 as the sum yk =Σha'Xk-n', n"" (iT-1)N
+11(5)n':1 cutlery, resulting in a pseudo echo signal. This pseudo echo signal y and the transmission signal yk of the terminal 3 are divided by a subtracter 9 into a difference e
k ek=YkYh (61 is taken and the residual signal e, which becomes the residual signal, is the second
input terminal and terminal 4. The above operation is carried out in one second, and the selector of each unit sends the received signal at terminal 1 or the data of the previous stage unit to the output of the memory at intervals of T seconds and for the first approximately T12N seconds. , and the oldest contents will be ejected. During the remaining time, the output signal of the selector data memory is selected.

In this way, the transversal filter with the number of taps is M
By cascading the stages, the whole operates like a transversal filter with MN taps.

Moreover, since the calculation time is 1 second regardless of the number of units, a transversal filter with a long tap length and a transversal with a high sampling frequency can be realized.

However, these conventional techniques have the following drawbacks. The first drawback is that the tap slice unit has a built-in accumulator, so the circuit configuration of the unit is complicated.

The second drawback is that since the summation of partial sums is performed by parallel addition, the circuit configuration becomes complicated as the number of units increases.

[Purpose of the invention]

The present invention improves the above-mentioned drawbacks of the prior art, and
The purpose is to provide a transversal filter that can be constructed from a tap slice unit with a simple circuit configuration.

[Summary of the invention]

A transversal filter according to the present invention includes a data memory for storing input signals, a coefficient memory for storing tap coefficients, and a multiplier for multiplying the outputs of the two memories.
It is characterized by comprising an accumulator that adds up the products of the multipliers for each bit to obtain a total sum.

[Embodiments of the invention]

The details of the present invention will be explained below with reference to the drawings.

FIGS. 3 and 4 show embodiments of the present invention, in which a tap slice unit is applied to an echo canceller as in the conventional example. The same symbols as in FIGS. 1 and 2 represent the same circuits. Adder 81. The shift register 82 is an achievable
Make up cod.

The operations in FIGS. 3 and 4 are as follows.

The first input terminal 100 is connected to the first output terminal of the previous unit, and the selector 16 selects whether the input signal Xp (p=k(b 1 ) x ) at the terminal 100 or the data memory 10
Select output signal X, -0 of data memo IJIOK
supply The output signal of the data memory 10 is transmitted to the first output terminal 101. Coefficient correction amount calculator 122 multiplier 14. The signal is supplied to the selector 16. Terminal 101 is connected to the first input terminal of the subsequent unit. The arithmetic unit 12 calculates the coefficient correction amount Δhg〇(g=(L-t)N) from the output signal X, -1 of the data memory 10 and the residual signal ek input from the second input terminal 102. The calculated formula (21) is supplied to the adder 13. The adder 13 corrects the output signal of the coefficient memory 11 and supplies +□ to the formula (31L) to the multiplier 14 and the coefficient memory 11. The product with the output Cg + a is yir=hg+."p-n+"=
1.2. -2N (force is supplied to the second output terminal 103. It is a feature of the present invention that this product is output from each unit.

The product I of each unit 71+, 71+, 7M is processed by an adder 81. An accumulator consisting of a shift register 82 calculates the sum for each bit to obtain a total sum ykΔ
NM Yh=Σ(,Σh(L 1)N+n−Xk(,i, 1
)N-n)n=1,=l=,Σh,'XBB-,/,n'=(L-
1) N ten n (13) n=1 is taken, resulting in a pseudo echo signal.

Figure 5 is 3. This explains the operation in Figure 4, and (
娨* (b+t (ci is the 1st stage, 2nd stage, Mth
The output YL/l (d) obtained by multiplying the input signal Xkj of the stage unit by the tap coefficient multiplied by 7 is the output y of the accumulator 8.

It is. The multiplication output yL/ is successively accumulated in each bit. This pseudo echo signal y and the transmission signal yk of the terminal 3 are subtracted by a subtracter 9 (Equation 6), and the residual signal ek is divided into each unit. is input to the second input terminal of K, and is also supplied to terminal 4, so that an echo-free transmission signal from the near-end terminal is sent to the far-end terminal. The above product-sum calculation and tap coefficient correction calculation are performed in T seconds, and the received signal at terminal 1 and the output signal from the data memory of the preceding unit are input to the data memory of each unit.

By cascading the tap slice units with N taps in M stages and accumulating and adding the product outputs of each unit, the entire filter operates like a transversal filter with MN taps. The calculation time is constant regardless of the number of units. Therefore, it is possible to realize a transversal filter with a simple circuit configuration and a long tap length or a high sampling frequency without requiring an achievator for each unit or soto.

FIGS. 6 and 7 show other embodiments of the present invention.

The difference between this embodiment and the embodiments shown in FIGS. 3 and 4 described above is that M adders out of (M+1) adders are used to accumulate and add the product outputs of each tap slice unit. 1
Each unit is stored one by one. This embodiment is mostly the same as the embodiment described above, so the explanation will focus on the differences. The adder 17 and the third input terminal 104 are circuits added to calculate the sum of the product outputs of each unit.

The output terminal of the multiplier is connected to one input terminal of the adder 17, the third input terminal 104 is connected to the other input terminal button, and the second output terminal 103 is connected to the output terminal. . The third input terminal 104 is connected to the second output terminal of the former unit, and the second output terminal 103 is connected to the third input terminal of the latter unit. The second output terminal of the final stage unit is connected to the input terminal of an amulator composed of an adder 81 and a shift register 82. As is clear from this configuration, the adder 17 of the first stage unit has the output of the data memory up to the (''-1)th stage and the output of the coefficient memory y4-1 (formula 8) and the adder 17 of the first stage unit. Take the sum of each bit with the product y- of the row unit,
The output is supplied to the (=+1)th stage. therefore,
At the output of the accumulator 8, each unit 7o, 7.
, 7M (Equation 9) is obtained, so it is sufficient to supply this to the subtractor 9.

In this embodiment as well, a transversal filter having the same effect as in the previously described embodiment can be obtained.

In the above embodiments, the example of application to an echo canceller has been described, but the present invention can be applied to various applications such as an automatic equalizer. In particular, when a fixed cod coefficient is applied to a transversal filter, the coefficient correction amount calculator of the tap slice unit is not necessary. Further, although the above explanation has been about serial calculations, parallel calculations are also possible.

〔Effect of the invention〕

According to the present invention, since an achievator is not required in each unit, a transversal filter with a simple circuit configuration and a long tap length or a transversal filter with a high sampling frequency can be obtained.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams of a conventional transnomous filter, and FIGS. 3 and 4 are block diagrams of an embodiment of the present invention.
FIG. 5 is an explanatory diagram of the operation of this embodiment, and FIGS. 6 and 7 are configuration diagrams of other embodiments of the present invention. 71+72+7M...Tap slice unit 81・
... Adder 82 ... Shift register 9 ... Subtractor
10...Data memory 11...Coefficient memory 1
2... Coefficient correction amount calculator 13... Adder 14
... Multiplier 17/Adder

Claims (1)

[Claims] In a transversal filter configured by cascading units having the same circuit configuration, each unit has a first input terminal for inputting a first signal and a memory for storing the first signal. a first memory for storing a second signal, a multiplier for multiplying the first signal and the second signal, and a pad for outputting the output of the multiplier.
and a second output terminal that selects and outputs a predetermined past signal from the internal signals of the first memory, and the second output terminal is connected to the first input terminal of the rear step unit. 1. A transversal filter comprising: an accumulation adder which is connected to the first output terminal and sums the multiplication outputs output from the first output terminal.