JPS6334646B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transversal filter used in automatic equalizers such as echo cancelers and modem modulators (MODEM) used in telephone lines having echoes.

Conventionally, in lines with echoes, echo suppression devices (echo suppressors) are used to control echoes.
However, since the line is turned ON and OFF, problems such as disconnection at the beginning of the line and clicking noise occur. The echo canceller is
It was developed to compensate for the drawbacks of such echo blocking devices. This device uses a filter having the same characteristics as the echo path existing therein to create an approximate echo signal similar to the echo signal, thereby canceling the actual echo signal. This echo cancellation device is generally digitalized to stabilize the device, and a transversal filter is used to create an approximate echo signal. The number of taps required in this transversal filter varies depending on the characteristics of the echo path.
Conventionally, it is technically difficult to change the number of taps according to the echo path characteristics, so the maximum number of taps considered necessary is set as the number of taps of the echo canceller. Therefore, the influence of quantization noise of the transversal filter is determined by the maximum number of taps, regardless of the required number of taps.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a transversal filter with a variable number of taps.

Next, the present invention will be explained in detail with reference to the drawings.
FIG. 1 shows a transversal filter 10 of the present invention.
FIG. 2 is a block diagram showing a first embodiment in which 0 is applied to an echo canceling device. First, the receiving side signal X' supplied from the receiving side input terminal 1 and the transmitting side signal Y' from the transmitting side input terminal 3 are sent to the analog-to-digital converter 5.
are converted into digital signals X and Y, respectively. This digital signal X is input to the receiving side signal storage circuit 9. The receiving side signal storage circuit 9 includes a tap coefficient storage circuit 8, a multiplication circuit 10, and an accumulator 11.
Together with this, they constitute a transversal filter. In this transversal filter, convolution integration is performed between the tap coefficient H _j from the tap coefficient storage circuit 8 and the received signal X _oj from the receiving side signal storage circuit 9 as shown in the following equation.

Y _o = _N 〓 ^j=k+1 H _j ·X _oj (1) Here, n is the time slot, j is the tap number, N is the number of taps, and Y _o is the output of the digital filter. The output Y _o of this transversal filter is an approximate echo signal, and the adder 7 subtracts the filter output from the transmitting side signal to cancel the echo. However, in a transversal filter, the quantization noise generated by the product of H _j and X _oj increases when integration is performed, so there is quantization noise equivalent to the number of taps N. Therefore, when the number of required taps is smaller than the number of taps of the transversal filter, it is expected that the characteristics of the echo canceling device will be improved by reducing the number of convolution integrals.

Here, by transforming equation (1) as equation (2) and setting the second term on the right side of equation (2) to 0, the number of taps can be varied in an equalizing manner, reducing the influence of quantization noise. I know what I can do.

Y= _k 〓 ^j=1 H _j・X _oj + _N 〓 ^j=k+1 H _j・X _oj 0<k<N (2) In the embodiment of the present invention shown in FIG. The tap coefficient of the first tap is read out from the tap coefficient storage circuit 8, the receiving side signal corresponding to the tap coefficient of the first tap is read out from the receiving side signal storage circuit 9, and the multiplication circuit 10 multiplies the tap coefficients. Then, the accumulator 11 calculates the sum of the outputs of the multiplication circuits from the first tap to the Nth tap. Now, when the product sum of the tap coefficient and the receiving side signal has progressed to k taps and the tap coefficient of the k+1st tap and the receiving side signal corresponding to the k+1st tap are to be read out, if the switch 12 is switched, the k+1th tap is read out.
Switch 1 instead of reading the tap coefficient of the tap.
By reading the 0 switched by 2, the product of the k+1 tap becomes 0. Similarly, while switching the switch 12, tap the k+1st to Nth taps.
If we calculate the sum of products up to the tap, the second term on the right side of equation (2) is 0.
becomes.

As mentioned above, the switching device 12 is controlled by a control circuit consisting of, for example, a counter and a comparison circuit that compares the counted value of this counter with a threshold value K, since it is sufficient to generate a switching signal at tap K+1. This can be done by preparing a switch 12 and switching the switch 12 in response to a match signal output from a comparator circuit when the counter counts up to the number of taps K.

FIG. 2 is a block diagram showing a second embodiment of the invention. In the embodiment shown in FIG. 2, the same calculation as in the embodiment shown in FIG.
The second term on the right side of equation (2) is set to 0 by switching the output of the memory circuit 9 to 0 while performing calculations from the k+1st to the Nth tap.

FIG. 3 shows a third embodiment of the present invention, and this embodiment also performs the same calculation as the embodiment of FIG.
By arranging the switch 14 between the multiplication circuit 10 and the accumulator 11, and setting the inputs to the accumulator 11 from the k+1st to the Nth tap to 0 by the switch 14, equation (2) can be obtained. The second term on the right side is set to 0.

FIG. 4 shows a fourth embodiment of the present invention, and shows an embodiment in which the present invention is applied to an adaptive echo canceler. In an adaptive echo canceler, the tap coefficient is generally modified using equation (3). There is.

Here, α is a correction coefficient, and e _o is an erasure signal that is the output of the subtracter 7.

The number of taps in the adaptive echo canceller is varied in the same way as in FIGS. The corresponding receiving side signal is switched to the switch 16.
Therefore, it is set to 0. By doing this, the k- _th + of the sum of squares ( _N 〓 ^{j= 1}
The portion corresponding to the 1st to Nth taps can be set to 0.

In the above embodiments, the application to an echo canceling device has been described, but the present invention can also be applied to an automatic equalizer such as a MODEM, an automatic equalizer that equalizes line distortion of data during data transmission, and the like.

FIG. 5 is a specific circuit diagram of the tap coefficient storage circuit 8. This memory circuit 8 is an N-stage shift register or RAM (random access memory) R ₁
〜R _N+1 , etc., and one cycle (j in equation (1)
completes the calculation from 1 to N) After completion, the original data is output. At the beginning of one cycle, the tap coefficient _H1 is stored in the first stage _R1 of the register. After the calculation between this tap coefficient _H1 and the received signal X _o-1 is completed, the tap coefficient is shifted by one stage,
This tap coefficient H ₁ is stored in the N-th register R _N , and the tap coefficient H ₂ is input to the register R ₁ . The reception signal storage circuit 9 also operates in a similar manner, and the signal
Output X _o-2 . After this calculation between H ₂ and X _o-2 is completed, another shift is performed by one stage. This is repeated, and after one cycle, the coefficient _H1 has been input to the register _R1 .

FIG. 6 is a specific circuit diagram of the receiving side signal storage circuit. It operates almost the same as the tap coefficient storage circuit 9. However, the length of the register is made one step longer or shorter than the memory circuit 9. (If one step is shorter, the calculation must be performed in reverse from the N-th tap to the 1st tap.) It also has a selector S _l for inputting new data.

At the beginning of one cycle, the selector S _l selects the B input, that is, the reception signal X _o-1 . This output is input to the register R _N+1 at the same time as the calculation is performed with the tap coefficient H ₁ . From the next calculation, the selector S _l selects the A input, so the output is X _o-2
......X _oN is output in order, and one cycle ends when X _oN is output. At this time, X _o-1 is a register
It is input to _R2 (because it is synchronized with the tap coefficient storage circuit, the register advances only N stages during one cycle, so it shifts by one stage at the beginning and end of one cycle). Furthermore, X _o-N+1 is input to register _R1 . This data is rewritten when a new reception signal X _o is input.

FIGS. 7a and 7b are specific circuit diagrams of the switching devices 12 and 13.

The input signal is output as is from the 1st tap to the kth tap, but 0 is output from the k+1 tap to the Nth tap. As a circuit, a configuration can be adopted in which input data is passed through a gate as shown in FIG. 7a, or switched by a selector S as shown in FIG. 7b. In FIG. 7a, 0 is output for taps 1 to k and taps k+1 to N.
Further, in FIG. 7b, the A input is selected for taps 1 to k, and the B input is selected for taps k+1 to N.

As described above, according to the present invention, it is possible to increase the amount of echo cancellation by reducing the influence of quantization noise. In addition, in the adaptive echo canceller, the second right-hand side of equation (3)
The correction speed becomes faster because the denominator of the term becomes smaller.

As a method for varying the number of taps in the adaptive echo canceller, the methods shown in FIGS. 2 and 3 can also be adopted.

[Brief explanation of the drawing]

1 to 4 are block diagrams showing first to fourth embodiments of the present invention, and FIGS. 5 to 7 are specific circuit diagrams showing a part of the present invention. In FIGS. 1 to 4, 1... Receiving side input terminal, 2... Receiving side output terminal, 3... Sending side input terminal, 4... Sending side output terminal, 5... Analog-digital converter, 6...Digital-to-analog converter, 7...Adder, 8...Tap coefficient storage circuit,
9... Receiving side signal storage circuit, 10... Multiplication circuit, 11... Accumulator, 12, 13, 14, 16...
...Switcher, 15...Tap gain correction circuit.

Claims (1)

[Claims] 1. A coefficient memory for storing coefficients, a data memory for storing data, a multiplier for multiplying the coefficient by the data, and an accumulator for accumulating the output of the multiplier. Yn＝ _k 〓 ^j=1 H _j X _oj + _N 〓 ^j=k+1 H _j X _oj (However, Yn is the filtering output, H _j is the jth coefficient, and X _oj is data before the jth
N is the number of filter taps) In a transversal filter that calculates the number of filter taps, there is a switching circuit that controls the result of _N 〓 ^j=k+1 H _j X _oj to be zero, and a control circuit that controls this switching circuit. and the switching circuit is arranged between the coefficient memory and the multiplier, between the data memory and the multiplier, or between the accumulator and the multiplier. Transvasal filter.