JPS6076174A - Bidirectional zener diode - Google Patents
Bidirectional zener diodeInfo
- Publication number
- JPS6076174A JPS6076174A JP18411083A JP18411083A JPS6076174A JP S6076174 A JPS6076174 A JP S6076174A JP 18411083 A JP18411083 A JP 18411083A JP 18411083 A JP18411083 A JP 18411083A JP S6076174 A JPS6076174 A JP S6076174A
- Authority
- JP
- Japan
- Prior art keywords
- type
- semiconductor wafer
- zener diode
- semiconductor element
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000001681 protective effect Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産梁上の利用分野
この発明は温度補償回路等に使用される双方向ツェナー
ダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Application in Industrial Beams This invention relates to bidirectional Zener diodes used in temperature compensation circuits and the like.
口、従来技術
順方向、逆方向共にブレークダウン電圧（ツェナー電圧
）を持つ双方向ツェナーダイオード素子の代表二個を第
１図と第２図により説明する。第１図は１つの半導体素
子（１）の表裏両面にＰＮジャンクション（２）（３）
とバンブ電極（４）（５）を形成した双方向ツェナーダ
イオード素子例を示す。具体的には例えばＮ型半導体素
子（１）の表裏両面の中央部にＰ型の不純物選択拡散で
形成されたＰ型領域（６）（７）上にバンブ電極（４）
（５）を形成したもので、一方のバンブ電極（４）にプ
ラス電圧を他方のバンブ電極（５）にマイナス電圧を加
えるとプラス側のＰＮジャンクション（２）が順方向、
マイナス側のＰＮジャンクション（３）が逆方向にバイ
アスされることになり、マイナス側のＰＮジャンクショ
ン（３）でブレークダウンが発生し、逆の電圧印加の時
にはＰＮジャンクション（２）でブレークダウンが発生
する。尚、第１図の（８）（９）は半導体素子（１）の
表裏両面の絶縁保護膜でこれを選択的に除去して、バン
ブ電極（４）（５）が形成される。Two typical prior art bidirectional Zener diode elements having breakdown voltages (Zener voltages) in both forward and reverse directions will be explained with reference to FIGS. 1 and 2. Figure 1 shows PN junctions (2) (3) on both the front and back sides of one semiconductor element (1).
An example of a bidirectional Zener diode element in which bump electrodes (4) and (5) are formed is shown. Specifically, for example, bump electrodes (4) are formed on P-type regions (6) and (7) formed by selective diffusion of P-type impurities in the center of both the front and back surfaces of the N-type semiconductor element (1).
(5), and when a positive voltage is applied to one bump electrode (4) and a negative voltage is applied to the other bump electrode (5), the positive side PN junction (2) moves in the forward direction.
The negative side PN junction (3) will be biased in the opposite direction, and a breakdown will occur at the negative side PN junction (3), and when the opposite voltage is applied, a breakdown will occur at the PN junction (2). do. Note that (8) and (9) in FIG. 1 are insulating protective films on both the front and back surfaces of the semiconductor element (1), and these are selectively removed to form bump electrodes (4) and (5).
まず、この第１図の双方向ツェナーダイオードの場合、
その製造は１″枚の半導体ウェーハ（図示せず）に多数
の半導体素子（１）（１）−を一括形成してから各素子
毎に細分割して行われるが、この細分割の際に半導体ウ
ェーハ表裏面に多数のバンブ電極（４）（４）・−・、
（５）（５） −が突出するため半導体ウェーハの保持
に特別な治具が必要であり、而も表裏面ともバンブ電極
の高さが完全には揃わず、安定に保持することが難しく
、そのためこの細分割時に、場合によっては、一部の素
子に不要な応力が集中し、半導体素子（１）に割れや欠
Ｌ）が発生し易く、実際十数％の割合で割れや欠けが発
生して歩留りが極めて悪かった。First, in the case of the bidirectional Zener diode shown in Figure 1,
Its manufacture is carried out by forming a large number of semiconductor elements (1) (1) - on a 1" semiconductor wafer (not shown) at once, and then subdividing each element. During this subdivision, A large number of bump electrodes (4) (4)... on the front and back surfaces of the semiconductor wafer.
(5) (5) - protrudes, so a special jig is required to hold the semiconductor wafer, and the bump electrodes are not perfectly aligned in height on both the front and back surfaces, making it difficult to hold it stably. Therefore, during this subdivision, in some cases, unnecessary stress concentrates on some elements, and cracks and chips (L) are likely to occur in the semiconductor element (1), and in fact, cracks and chips occur at a rate of more than 10%. The yield was extremely poor.
つぎに、第２図は１つの半導体素子（１０）の表面側に
１つのＰＮジャンクション（１１）とバンブ電極（１２
）を形成し且つ裏面に平坦な裏面電極（１３）を形成し
たツェナーダイオード素子（１４）を２個裏面電極（１
３） （１３）同士を圧着接合して一体化して１つの双
方向ツェナーダイオード素子（１５）としたものである
。この場合、両ツェナーダイオード素子（１４） （１
４）は一つの半導体ウェーハを多分割し接合して作成さ
れて各々のツェナー電圧を同一にすることができ、また
半導体ウェーハからの細分割は半導体ウェーハの裏面が
平坦なためその保持が容易で安定して行えるので高い歩
留りで製造できる。Next, FIG. 2 shows one PN junction (11) and bump electrode (12) on the front side of one semiconductor element (10).
) and a flat back electrode (13) on the back surface.
3) (13) are bonded together and integrated to form one bidirectional Zener diode element (15). In this case, both Zener diode elements (14) (1
4) is made by dividing one semiconductor wafer into multiple parts and bonding them together, making it possible to make the Zener voltage of each part the same, and it is easy to hold the semiconductor wafer by dividing it finely because the back surface of the semiconductor wafer is flat. Since it can be performed stably, it can be manufactured with a high yield.
しかし、各ツェナーダイオード素子（１４） （１４）
は０．５顛角以下程度の小さなものであり、而も片面に
バンブ電極（１２） （１２）を持つ形状のため、これ
を２個背面合せして接合一体化し双方向ツェナーダイオ
ードを組立る作業は非富に困難で作業性が極めて低く、
また、組立上、細分割寸法が不均一となることは避けら
れず、そのため接合した素子は、特性が変化して信頼性
に欠ける問題があった。However, each Zener diode element (14) (14)
is small, about 0.5 angle or less, and has a bump electrode (12) (12) on one side, so two of these are back-to-back and joined together to assemble a bidirectional Zener diode. The work is extremely difficult and the workability is extremely low.
Furthermore, during assembly, it is unavoidable that the dimensions of the subdivisions become non-uniform, and as a result, the characteristics of the joined elements change, resulting in a lack of reliability.
ハ１発明の目的
本発明は上記従来の各問題点に鑑みなされたもので、１
つの半導体素子の片面側に少くとも２まのＰＮジャンク
ションを形成することで上記各問題点を解決した双方向
ツェナーダイオ−Ｖを提供することを目的とする。C1 Purpose of the Invention The present invention has been made in view of the above-mentioned conventional problems.
It is an object of the present invention to provide a bidirectional Zener diode-V which solves the above problems by forming at least two PN junctions on one side of one semiconductor element.
二０発明の構成
本発明は双方向ツェナーダイオード素子の改良でありで
、１つの半導体素子の片面に順方向と逆方向の異なる２
つのＰＮジャンクションを形成し、片面側の電極は多結
晶シリコン層を介在させて設けたことを特徴とする。こ
のようにすると上記半導体素子はＰＮジャンクション形
成側片面に１つのバンブ電極を、反対面に平坦な電極を
形成する等して一般的ダイオード素子と同じ外観のもの
が得られ、製造が容易になる。また２つのＰＮジャンク
ションは同時に同一条件下で作成できて双方向特性の安
定したものが提供できる。20 Structure of the Invention The present invention is an improvement of a bidirectional Zener diode element, in which there are two different forward and reverse directions on one side of one semiconductor element.
It is characterized in that two PN junctions are formed, and the electrode on one side is provided with a polycrystalline silicon layer interposed therebetween. In this way, the semiconductor element has the same appearance as a general diode element by forming one bump electrode on one side of the PN junction formation side and a flat electrode on the other side, making it easier to manufacture. . Furthermore, two PN junctions can be created simultaneously under the same conditions, providing stable bidirectional characteristics.
ホ、実施例
第３図は本発明による双方向ツェナーダイオード素子（
１６）において、（１７）は−導電型の例えばＰ型の半
導体素子、（１８）は半導体素子（１７）の表面中央部
にＮ型不純物の選択拡散で形成したＮ型領域、（１９）
は、Ｎ型領域（１８）の中央部に１．そして（２０）は
Ｎ型領域（１Ｂ）の周辺部の内外に跨げて、それぞれＰ
型不純物の選択拡散で形成したＰ型領域で、中央部のも
のを第１Ｐ型領域（１９） 、周辺部のものをＮ５２Ｐ
型領域（２０）と称する。この各Ｐ型領域（１９）（２
０）は、後述する素子製造説明に示される第５図のよう
に、先ず第１、第２Ｐ型ガードリング域（１９”） （
２０’ ）を押込拡散で形成してがらその中に一定の深
さ、濃度で形成される。E. Example Fig. 3 shows a bidirectional Zener diode element (
In 16), (17) is a − conductivity type, for example, a P-type semiconductor element, (18) is an N-type region formed in the center of the surface of the semiconductor element (17) by selective diffusion of N-type impurities, and (19)
1 in the center of the N-type region (18). And (20) spans the inside and outside of the peripheral part of the N-type region (1B), and P
P-type regions formed by selective diffusion of type impurities, the central region is the first P-type region (19), and the peripheral region is N52P.
It is called a mold area (20). Each of these P-type regions (19) (2
0), as shown in FIG. 5 in the explanation of device manufacturing described later, first, the first and second P-type guard ring regions (19'') (
20') is formed by indentation diffusion, and is formed at a constant depth and concentration therein.
（２１）は半導体素子（１７）の表面に形成した絶縁保
護膜、（２２）は絶縁保護膜（２１）の中央部を選択的
に除去して露出した第１Ｐ型領域（１９）上に形成した
多結晶シリコン層、（２３）はさらにその上に形成した
バンブ電極、（２４）は半導体素子（１７）の裏面に形
成した平坦な裏面電極である。(21) is an insulating protective film formed on the surface of the semiconductor element (17), and (22) is formed on the first P-type region (19) exposed by selectively removing the central part of the insulating protective film (21). (23) is a bump electrode formed thereon, and (24) is a flat back electrode formed on the back surface of the semiconductor element (17).
第１Ｐ型領域（工９）とＮ型領域（１８）で１つのＰＮ
ジャンクションＪｌが形成され、第２Ｐ型領域（２０）
とＮ型領域（１８）でＮ型領域（１８）とＰ型半導体素
子（１７）間に形成されたＰＮＮジャンクシラン連結さ
れたＰＮジャンクションＪ２が形成され、以下前者を第
１ＰＮジャンクシッンＪｌ、後者を第２ＰＮジヤンクシ
ツンＪ２と称す、２つの第１１第２ＰＮジャンクシッン
Ｊｌ 、Ｊ２は順方向と逆方向の異なる方向性を有して
各々は直列状態に配され、仮りにバンプ電極（２３）に
プラス電圧を裏面電極（２４）にマイナス電圧を加える
と第１ＰＮジヤンクシヨンＪ１は順方向に第２ＰＮジヤ
ンクシヨンＪ２は逆方向になり、逆の電圧印加では第１
ＰＮジヤンクシヨンＪ１が逆方向に第２ＰＮジヤンクシ
ヨンＪ２が順方向になる。各ＰＮジャンクションＪｌ
、Ｊ２における耐圧は各ガードリング域（１９’ ）
（２０’ ）の部所が高く各Ｐ型領域（１９）（２０）
の底面とＮ型領域（１８）の接する図面太線部分が低（
、従って各ＰＮジャンクションＪ１、Ｊ２のブレークダ
ウン電圧は図面太線部分で決定され、この第１ＰＮジヤ
ンクシヨンＪｌでのブレークダウン電圧をＶｚｌ、第２
ＰＮジヤンクシロンＪ２でのブレークダウン電圧をＶｚ
２とするとバンプ電極（２３）にプラス電圧を印加した
時はＶｚ２のツェナー電圧特性が逆に裏面電極（２４）
にプラス電圧を印加した時はＶＺＩのツェナー電圧特性
が得られ、双方向ツェナーダイオードとして動作する。One PN in the first P-type region (technique 9) and N-type region (18)
Junction Jl is formed and the second P type region (20)
A PNN junction J2 is formed between the N type region (18) and the P type semiconductor element (17) in the N type region (18) and the N type region (18). The two eleventh second PN junks J2, referred to as second PN junks J2, have different directionality, forward and reverse, and are arranged in series, assuming that a positive voltage is applied to the bump electrode (23). When a negative voltage is applied to the back electrode (24), the first PN junction J1 moves in the forward direction and the second PN junction J2 moves in the opposite direction.
The PN junction J1 is in the reverse direction and the second PN junction J2 is in the forward direction. Each PN junction Jl
, the withstand voltage at J2 is in each guard ring area (19')
(20') is high in each P-type region (19) (20)
The thick line in the drawing where the bottom surface of the N-type region (18) touches is low (
, Therefore, the breakdown voltage of each PN junction J1, J2 is determined by the bold line part in the drawing, and the breakdown voltage at this first PN junction Jl is determined by Vzl, and the breakdown voltage at the second PN junction Jl is determined by
The breakdown voltage at PN Jyankushiron J2 is Vz
2, when a positive voltage is applied to the bump electrode (23), the Zener voltage characteristic of Vz2 will be reversed to the back electrode (24).
When a positive voltage is applied to the diode, it obtains the Zener voltage characteristics of VZI and operates as a bidirectional Zener diode.
上記双方向ツェナーダイオード素子（１６）は第４図乃
至第７図に示す要領で製造される。先ず第４図に示すよ
うに１枚のＰ型半導体ウェーハ（２５）を用意し、これ
の表面側に複数のＮ型領域（１Ｂ） （１Ｂ）−を一括
して形成する。次に半導体ウェーハ（２５）の表面から
Ｐ型不純物を選択的に押込拡散して第５図に示すように
複数のＰ型ガードリング域（１９’ ） （１９”）−
・、（２０’ ） （２０’ ） −を一括して形成し
、その後第６図に示すように各ガードリング域（１９°
）（１９°）・−・、（２０°）（２０°）−内にＰ型
領域（１９） （１９）−１（２０） （２０）−を同
一条件下で一括して形成する。而る後第７図に示すよう
に半導体ウェーハ（２５）の裏面全域に裏面電極（２４
）を形成し、表面のＰ型領域（１９） （１９）露出面
及びその周縁の絶縁保護膜（２１）上に、多結晶シリコ
ンＪｉｉ （２２） （２２）を付着させ、第１及び第
２のＰＮジャンクシッンＪｌ 、Ｊｌ、−Ｊ２ 、Ｊ２
、・−・の特性が同一となるように、不純物をドープ
させて抵抗値設定を行う、その後、Ｐ型領域（１９）
（１９）上に夫々、バンプ電極（２３） （２３）−・
を一括して形成してから、半導体ウェーハ（２４）を第
７図破線矢印から各半導体素子（１７） （１７）・−
毎に細分割する。The bidirectional Zener diode element (16) is manufactured in the manner shown in FIGS. 4 to 7. First, as shown in FIG. 4, one P-type semiconductor wafer (25) is prepared, and a plurality of N-type regions (1B) (1B)- are collectively formed on the front side of the wafer. Next, P-type impurities are selectively pushed and diffused from the surface of the semiconductor wafer (25) to form a plurality of P-type guard ring regions (19') (19'')- as shown in FIG.
, (20') (20') - are formed all at once, and then each guard ring area (19°
) (19°) - (20°) (20°) - P-type regions (19) (19) -1 (20) (20) - are formed all at once under the same conditions. After that, as shown in FIG. 7, a back electrode (24
), polycrystalline silicon Jii (22) (22) is deposited on the exposed surface of the P-type region (19) (19) and the insulating protective film (21) on its periphery, and the first and second PN Junk Shin Jl , Jl, -J2 , J2
, . . . dope with impurities and set the resistance value so that the characteristics of , . . .
(19) On top of each other are bump electrodes (23) (23)-.
After forming the semiconductor wafer (24) at once, each semiconductor element (17) (17) -
Subdivide each.
上記製造において、半導体ウェーッ＼（２５）への不純
物選択拡散は全て表面側に対してのみ行うので一般的ダ
イオードの製造と同様簡単で量産性良く行え、特に半導
体ウェーハ（２４）の細分割は第２図例と同様に歩留り
良く行える。また各Ｐ型領域（１９） （１９）−１（
２０） （２０）・−を同一条件下で同時に形成するの
で各々の深さや不純物濃度が均一になり、しかも多結晶
シリコン層（２２） （２２）により各ＰＮジャンクシ
ロン月、Ｊｌ、・・−・、Ｊ２ 、Ｊ２、−・−におけ
るブレークダウン電圧ＶＺＩ、 ＶＺＩ、 −１Ｖｚ２
、Ｖｚ２、−を同一にすること可能になり、双方向ツェ
ナーダイオードの特性著しい均一化が図れる。In the above manufacturing process, all selective diffusion of impurities into the semiconductor wafer (25) is performed only on the surface side, so it can be performed simply and with good mass productivity, similar to the manufacturing of general diodes.In particular, the fine division of the semiconductor wafer (24) is Similar to the example shown in Figure 2, it can be carried out with good yield. In addition, each P-type region (19) (19)-1(
20) Since (20) and - are formed simultaneously under the same conditions, the depth and impurity concentration of each are uniform, and the polycrystalline silicon layer (22) (22) makes each PN junction, Jl,... - Breakdown voltage VZI, VZI, -1Vz2 at ・, J2, J2, ---
, Vz2, - can be made the same, and the characteristics of the bidirectional Zener diode can be significantly uniformized.
尚、本発明は上記実施例に限らず、上記実施例のＰ型を
Ｎ型、Ｎ型をＰ型にして構成してもよく、また半導体素
子表面側に平坦電極を裏面側にバンプ電極を形成する等
の変更も可能である。It should be noted that the present invention is not limited to the above-mentioned embodiments, but may be configured such that the P-type in the above-mentioned embodiments is replaced by an N-type, and the N-type is replaced by a P-type, and a flat electrode is provided on the front side of the semiconductor element and a bump electrode is provided on the back side. It is also possible to make changes such as forming.
へ、発明の効果
以上の如く、本発明によれば双方向ツェナーダイオード
素子の製造が容易で量産性、歩留りが向上し、また２つ
のＰＮジャンクションの同一条件下での同時形成ができ
特性の均一化が可能となり、安価な高信頼度の双方向ツ
ェナーダイオードが提供できる。B. Effects of the Invention As described above, according to the present invention, it is easy to manufacture a bidirectional Zener diode element, improving mass productivity and yield, and two PN junctions can be formed simultaneously under the same conditions, resulting in uniform characteristics. This makes it possible to provide inexpensive and highly reliable bidirectional Zener diodes.
第１図及び第２図は従来の双方向ツェナーダイオード素
子を示す各断面図、第３図は本発明の一実施例を示す双
方向ツェナーダイオード素子断面図、第４図乃至第７図
は第３図に示した双方向ツェナーダイオードの製造工程
を説明する各工程における半導体ウェーハ部分断面図で
ある。
（１７）・・半導体素子、Ｊｌ 、Ｊ２ ・・ＰＮジャ
ンクシ目ン、（２２）・・多結晶シリコン層、（２３）
・・片面側のバンプ電極。
第１図 第２図
第３図1 and 2 are cross-sectional views showing a conventional bidirectional Zener diode element, FIG. 3 is a cross-sectional view of a bidirectional Zener diode element showing an embodiment of the present invention, and FIGS. FIG. 4 is a partial cross-sectional view of a semiconductor wafer in each step for explaining the manufacturing process of the bidirectional Zener diode shown in FIG. 3; (17)...Semiconductor element, Jl, J2...PN junction, (22)...Polycrystalline silicon layer, (23)
...Bump electrode on one side. Figure 1 Figure 2 Figure 3
Claims (1)
る２つのＰＮジャンクションを形成し、片面側の電極は
多結晶シリコン層を介在させて設けたことを特徴とする
双方向ツェナーダイオード。(l) A bidirectional Zener diode characterized in that two PN junctions in different forward and reverse directions are formed on one side of one semiconductor element, and an electrode on the one side is provided with a polycrystalline silicon layer interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18411083A JPS6076174A (en) | 1983-09-30 | 1983-09-30 | Bidirectional zener diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18411083A JPS6076174A (en) | 1983-09-30 | 1983-09-30 | Bidirectional zener diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6076174A true JPS6076174A (en) | 1985-04-30 |
Family
ID=16147560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18411083A Pending JPS6076174A (en) | 1983-09-30 | 1983-09-30 | Bidirectional zener diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076174A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430311A (en) * | 1991-09-20 | 1995-07-04 | Hitachi, Ltd. | Constant-voltage diode for over-voltage protection |
| CN101916786A (en) * | 2010-06-22 | 2010-12-15 | 南通明芯微电子有限公司 | High-power planar junction bidirectional TVS diode chip and production method thereof |
-
1983
- 1983-09-30 JP JP18411083A patent/JPS6076174A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430311A (en) * | 1991-09-20 | 1995-07-04 | Hitachi, Ltd. | Constant-voltage diode for over-voltage protection |
| CN101916786A (en) * | 2010-06-22 | 2010-12-15 | 南通明芯微电子有限公司 | High-power planar junction bidirectional TVS diode chip and production method thereof |
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