JPS5821865A - Constant-current diode - Google Patents

Constant-current diode

Info

Publication number
JPS5821865A
JPS5821865A JP11918481A JP11918481A JPS5821865A JP S5821865 A JPS5821865 A JP S5821865A JP 11918481 A JP11918481 A JP 11918481A JP 11918481 A JP11918481 A JP 11918481A JP S5821865 A JPS5821865 A JP S5821865A
Authority
JP
Japan
Prior art keywords
layer
diffused layer
region
diffusion layer
type diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11918481A
Other languages
Japanese (ja)
Inventor
Tadao Takano
高野 忠夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Rectifier Corp Japan Ltd
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp Japan Ltd
Infineon Technologies Americas Corp
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp Japan Ltd, Infineon Technologies Americas Corp, International Rectifier Corp USA filed Critical International Rectifier Corp Japan Ltd
Priority to JP11918481A priority Critical patent/JPS5821865A/en
Publication of JPS5821865A publication Critical patent/JPS5821865A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/868PIN diodes

Abstract

PURPOSE:To increase the distance between both electrode metals of a constant-current diode by isolating and forming part of a diffused layer becoming a gate region and a diffused layer becoming a source region so as to alternately intrude in a circumferential direction to each other and forming a stepwise difference between a connecting electrode metal on the region and a drain electrode metal. CONSTITUTION:On a P type semiconductor substrate 21 is grown an N type epitaxial layer 22 having a flat raised top shape, in the layer 22 are further formed an annular P type diffused layer 23 becoming a gate region and an N type diffused layer 24 becoming a source region, and at the center is formed an N type diffused layer 24 becoming a drain region. A plurality of rectangular P type diffused layers 23a are formed at the prescribed interval circumferentially on the layer 23, thereby forming a P type diffused layer 23b passing through the substrate 21 connected to the layer 23a. An N type diffused layer 25 formed in the adjacent region formed with the layers 23, 23a and 23b is formed of an N type diffused layer 24a corresponding to the layers 23a, 23b and an N type diffused layer 24b extending to the substrate 21. In this manner, an electrode metal 27 and an annular connecting metal 28 are formed through an insulating layer 26 such as an SiO2 on the substrate 21, the layers 24b, 23b, thereby completing a constant- current diode having stepwise difference between both electrodes.

Description

【発明の詳細な説明】 極金属間の短絡事故を防止し得る電極構造に係る。[Detailed description of the invention] This invention relates to an electrode structure that can prevent short-circuit accidents between polar metals.

定電流ダイオードの概略構成を第1図に示す。FIG. 1 shows a schematic configuration of a constant current diode.

同図において、P 半導体基板1上に、N−エピタキシ
ャル層2を成長させ、このエピタキシャル層2中にゲー
ト領域となるP拡散層、ソース領域となるN 拡散層4
及びドレイン領域となるN+4−拡散層5が、一般的に
良く知られた選択拡散方法により形成される。そして前
記基板1の一方の主面から拡散が施されてアイソレイシ
ョン拡散層6が形成され島状に分離されている。
In the figure, an N epitaxial layer 2 is grown on a P semiconductor substrate 1, and in this epitaxial layer 2, a P diffusion layer becomes a gate region, and an N diffusion layer 4 becomes a source region.
And an N+4- diffusion layer 5, which becomes a drain region, is formed by a generally well-known selective diffusion method. Then, diffusion is performed from one main surface of the substrate 1 to form an isolation diffusion layer 6, which is separated into islands.

上記基板1の一方の主面には、電極金属7が、他方の主
面には、P拡散層3上のSiO2膜等から成る絶縁層8
の一端とオーバーランプしてN 拡散層5上に電極金属
9が、また、P拡散層6、N++拡散層及びP拡散層3
を短絡する連結用電極金属10がそれぞれ設けられてい
る。
An electrode metal 7 is formed on one main surface of the substrate 1, and an insulating layer 8 made of a SiO2 film or the like on the P diffusion layer 3 is formed on the other main surface.
An electrode metal 9 is placed on the N diffusion layer 5 overlapping with one end, and the P diffusion layer 6, the N++ diffusion layer and the P diffusion layer 3 are also placed on the N diffusion layer 5.
Connecting electrode metals 10 for short-circuiting are respectively provided.

上記の構成において、定電流ダイオードとして゛の所定
の電気的特性を得るためにゲート領域と々るP+拡散層
3の直下のチャンネル長が必然的に制約を受け、N 拡
散層5上の電極金属9と連結用電極金属10とが100
〜150μm程度の極めて接近した距離となり、短絡事
故等を招来し、信頼性の点で問題があった。特に、生産
性の向上の見地から第2図に示すようにリード11及び
12のアキシャル化が望まれるが、この場合に、半導体
ペレット13上に形成した前記電極金属9及び10が接
近しているだめにリード11の寸法精度を厳密に、かつ
所定の位置に正確に位置決めして固定しなければならず
、生産性を改善するだめの問題点の1つとなっていた。
In the above configuration, in order to obtain predetermined electrical characteristics as a constant current diode, the channel length directly under the P+ diffusion layer 3 reaching the gate region is inevitably restricted, and the electrode metal on the N diffusion layer 5 is restricted. 9 and the connecting electrode metal 10 are 100
The distance was extremely close to about 150 μm, which caused short circuit accidents and other problems in terms of reliability. In particular, from the viewpoint of improving productivity, it is desirable to make the leads 11 and 12 axial as shown in FIG. 2, but in this case, the electrode metals 9 and 10 formed on the semiconductor pellet 13 are close to each other. In order to do so, the lead 11 must be precisely positioned and fixed at a predetermined position with strict dimensional accuracy, which is one of the problems in improving productivity.

本発明は、上記の事情に基づきなされたもので、ゲート
領域となるP拡散層の一部をソース領域となるN++拡
散層とを互いに入り込ませたパターン形状とし、かつソ
ース領域及びゲート領域上の電極金属とドレイン領域上
の電極金属との間に段差を設け、両電極金属間の距離を
従来に比し大きくとり得るようにした定電流ダイオード
を提供することを目的とする。
The present invention has been made based on the above-mentioned circumstances, and has a pattern shape in which a part of the P diffusion layer that will become the gate region and the N++ diffusion layer that will become the source region are interwoven with each other. It is an object of the present invention to provide a constant current diode in which a step is provided between an electrode metal and an electrode metal on a drain region, so that the distance between both electrode metals can be made larger than in the past.

以下に、本発明の実施例を図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.

第3図は、本発明の第1の実施例を示す斜視図、第4図
は、第3図のX−Y−Z線に沿う断面図である。
FIG. 3 is a perspective view showing the first embodiment of the present invention, and FIG. 4 is a sectional view taken along the X-Y-Z line in FIG. 3.

同図において、P 半導体基板21上に、頂面が平坦な
山形状のN−エピタキシャル層22を成長させ、このエ
ピタキシャル層22内にゲート領域となる環状P拡散層
23及びソース領域となるN++拡散層24と、さらに
その中心部にドレイン前記環状P拡散層23の円周方向
に所定の間隔を隔てて複数の短冊状のP拡散層23aを
形成し、さらにこの拡散層23aに連ねて前記P 半導
体基板21に通じるP拡散層23bを形成する。
In the figure, a mountain-shaped N- epitaxial layer 22 with a flat top surface is grown on a P semiconductor substrate 21, and within this epitaxial layer 22 are formed an annular P diffusion layer 23 that will become a gate region and an N++ diffusion layer that will become a source region. A plurality of strip-shaped P diffusion layers 23a are formed in the center of the layer 24 at predetermined intervals in the circumferential direction of the drain annular P diffusion layer 23, and the P diffusion layers 23a are further formed in series with the diffusion layer 23a. A P diffusion layer 23b communicating with the semiconductor substrate 21 is formed.

上記環状P拡散層23、短冊状のP拡散層23a及び2
3bによって形成される隣接領域に形成されたN 拡散
層25は、前記P拡散層23a及び23bに対応してN
 拡散層2’4aとP 半導体基板21寸で延びるN 
拡散層24bとから成る0 しかして、5i02等の絶縁層26を介して、電極金属
27及び環状連結用金属28をP 半導体基板21、N
 拡散層24b%P拡散層23b上に設けることにより
、図示の如く、両電極間に段差のある定電流ダイオード
が完成する。
The annular P diffusion layer 23, the strip-shaped P diffusion layers 23a and 2
The N diffusion layer 25 formed in the adjacent region formed by the N diffusion layer 3b corresponds to the P diffusion layer 23a and 23b.
Diffusion layer 2'4a and P N extending by 21 dimensions of semiconductor substrate
Therefore, the electrode metal 27 and the annular connection metal 28 are connected to the semiconductor substrate 21, N through the insulating layer 26 such as 5i02, and the diffusion layer 24b.
By providing the diffusion layer 24b% on the P diffusion layer 23b, a constant current diode with a step between both electrodes is completed as shown in the figure.

上記の構成により、電極金属27と環状連結用金属28
との間には段差が設けられ、両電極間の距離を比較的大
きくとることが可能になることから短絡事故等のおそれ
が回避される。したがってアキシャル型の定電流ダイオ
ードの生産性を白土させ得る。さらに従来の如くPアイ
ソレイション拡散層の形成が不要となると共にチャンネ
ル幅(ドレイン領域中心からゲート領IJ12tでの半
径)が比較的自由に選定でき、アキシャル型定電流ダイ
オードの実現に寄与するところ大である。
With the above configuration, the electrode metal 27 and the annular connection metal 28
Since a step is provided between the two electrodes, it is possible to maintain a relatively large distance between the two electrodes, thereby avoiding the possibility of a short circuit accident or the like. Therefore, the productivity of axial type constant current diodes can be improved. Furthermore, it is not necessary to form a P isolation diffusion layer as in the past, and the channel width (radius from the center of the drain region to the gate region IJ12t) can be selected relatively freely, which greatly contributes to the realization of an axial type constant current diode. It is.

第5図は、本発明の第2の実施例を示す斜視図である。FIG. 5 is a perspective view showing a second embodiment of the invention.

この実施例では、環状P拡散層23から延びた短冊状の
P+拡散層23a及び23bに当るP++半導体基板2
1のコーナ部を切欠し、短絡部29を形成したもので、
第1の実施例と同様の効果を有すると共に製造工程の簡
略化等が期待できる。
In this embodiment, the P++ semiconductor substrate 2 corresponds to the strip-shaped P+ diffusion layers 23a and 23b extending from the annular P diffusion layer 23.
The corner part of 1 is cut out to form a short circuit part 29,
It can be expected to have the same effects as the first embodiment and to simplify the manufacturing process.

なお、同図において第1の実施例と同一部分には同一符
号を付してその詳しい説明は省略する。
In the figure, the same parts as in the first embodiment are given the same reference numerals, and detailed explanation thereof will be omitted.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の定電流ダイオードの構造の一例を示す
概略構成図、第2図は、上記構成の半導体ベレットを用
いてアキシャル型に形成した定電流ダイオードの概略構
成図、第3図は、本発明の第1の実施例を示す定電流ダ
イオードの半導体ペレットの斜視図、第4図は、第3図
のx−y−z線に沿う断面図、第5図は、本発明の第2
の実施例を示す前記第3図同様の半導体ベレットの斜視
図である。 21・・・P 半導体基板、 22°・・N−エピタキシャル層、 23・・・環状P拡散層、 24・・・N 拡散層、  25・・・N 拡散層、2
6・・・絶縁層、    27・・・電極金属、28・
・・環状連結用電極金属、 29・・・短絡部。
FIG. 1 is a schematic configuration diagram showing an example of the structure of a conventional constant current diode, FIG. 2 is a schematic configuration diagram of a constant current diode formed in an axial type using a semiconductor pellet with the above configuration, and FIG. 3 is a schematic configuration diagram showing an example of the structure of a conventional constant current diode. , FIG. 4 is a perspective view of a semiconductor pellet of a constant current diode showing the first embodiment of the present invention, FIG. 4 is a sectional view taken along the x-y-z line of FIG. 3, and FIG. 2
FIG. 3 is a perspective view of a semiconductor pellet similar to that shown in FIG. 3, showing an embodiment of the present invention. 21...P semiconductor substrate, 22°...N-epitaxial layer, 23...annular P diffusion layer, 24...N diffusion layer, 25...N diffusion layer, 2
6... Insulating layer, 27... Electrode metal, 28...
... Electrode metal for annular connection, 29 ... Short circuit part.

Claims (1)

【特許請求の範囲】[Claims] ゲート領域となる拡散層の一部とソース領域となる拡散
層とを円周方向に交互に入り込む如く分離形成し、前記
ゲート領域及びソース領域上の連結用電極金属とドレイ
ン領域上の電極金属間に段差を設けたことを特徴とする
定電流ダイオード。
A part of the diffusion layer that will become the gate region and a diffusion layer that will become the source region are formed separately so as to intersect alternately in the circumferential direction, and a part of the diffusion layer that will become the gate region and a diffusion layer that will become the source region are formed separately so that they intersect with each other in the circumferential direction, and between the connecting electrode metal on the gate region and the source region and the electrode metal on the drain region. A constant current diode characterized by having a step.
JP11918481A 1981-07-31 1981-07-31 Constant-current diode Pending JPS5821865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11918481A JPS5821865A (en) 1981-07-31 1981-07-31 Constant-current diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11918481A JPS5821865A (en) 1981-07-31 1981-07-31 Constant-current diode

Publications (1)

Publication Number Publication Date
JPS5821865A true JPS5821865A (en) 1983-02-08

Family

ID=14754984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11918481A Pending JPS5821865A (en) 1981-07-31 1981-07-31 Constant-current diode

Country Status (1)

Country Link
JP (1) JPS5821865A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008282878A (en) * 2007-05-08 2008-11-20 Rohm Co Ltd Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008282878A (en) * 2007-05-08 2008-11-20 Rohm Co Ltd Semiconductor device and manufacturing method thereof

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