JPS6041265A - Diode - Google Patents
DiodeInfo
- Publication number
- JPS6041265A JPS6041265A JP14988583A JP14988583A JPS6041265A JP S6041265 A JPS6041265 A JP S6041265A JP 14988583 A JP14988583 A JP 14988583A JP 14988583 A JP14988583 A JP 14988583A JP S6041265 A JPS6041265 A JP S6041265A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- substrate
- resistance
- holes
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000006798 recombination Effects 0.000 abstract 1
- 238000005215 recombination Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
Description
【発明の詳細な説明】
本発明は超高周波帯で使用されるマイクロ波ダイオード
、特にＰＩＮダイオードに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microwave diode used in an ultra-high frequency band, and particularly to a PIN diode.
近年、超高周波帯装置のマイクロ波集積回路化に伴い、
用いられるダイオードは小形で浮遊リアクタンスが小さ
いこと、又実装が便利なこと等が要求されることから、
ビームリード形ダイオードが多く使用されている。特に
フェーズドアレイレーダーにおいては使用するＰＩＮダ
イオード素子の数量が多く、このシステムを集積化する
ためにはビームリード形ＰＩＮダイオードが望ましい。In recent years, with the development of microwave integrated circuits in ultra-high frequency band equipment,
The diodes used are required to be small, have low stray reactance, and be convenient to mount.
Beam lead type diodes are often used. Particularly in a phased array radar, a large number of PIN diode elements are used, and in order to integrate this system, a beam lead type PIN diode is desirable.
この目的に沿って種々のビームリード形ＰＩＮダイオー
ドが開発発表されている。この例を第１．２図に示す。Various beam lead type PIN diodes have been developed and announced for this purpose. An example of this is shown in Figure 1.2.
第１図は高抵抗シリコン基板１に要求特性に応じて所定
の間隔を開けてＰ 層２及びｎ 層３を拡散等によって
形成し、この２層２． ｎ 層３からそれぞれ絶縁膜６
上に形成された電極リード８に電極を取り出したもので
ある。これは構造的に簡単で量産性に適しているが深い
拡散層が得られないために直流および高周波信号に対す
る直列抵抗が太きくなるという欠点をもっている。In FIG. 1, a P layer 2 and an N layer 3 are formed by diffusion or the like on a high-resistance silicon substrate 1 at a predetermined interval according to required characteristics, and these two layers 2. Insulating film 6 from layer 3
The electrode is taken out from the electrode lead 8 formed above. Although this is structurally simple and suitable for mass production, it has the disadvantage that a deep diffusion layer cannot be obtained and the series resistance against DC and high frequency signals becomes large.
第２図は第１図の構造の場合とブレークダウン電圧、容
量等の点で同じ電気的特性を満足しかつ直列抵抗を減少
せんとするための構造である。これは第１図と同様に所
定の間隔をへだてた２層２゜ｎ 層３を形成する部分の
シリコン基板１にエツチングにて所定の深さのポケット
状の穴４を形成した後にＰ 層２． ｎ 層３をそれぞ
れ拡散等によって形成したものである。この構造は直流
および高周波信号に対する直列抵抗を減少することが出
来るがその製造が複雑化するとともにポケット状に開け
た穴４上の電極リード８が平面性を失ない、大端部にお
いて断切れを起こす等量産性には極めて不向きである。FIG. 2 shows a structure that satisfies the same electrical characteristics as the structure shown in FIG. 1 in terms of breakdown voltage, capacitance, etc., and is intended to reduce series resistance. This is done by etching a pocket-like hole 4 of a predetermined depth in the silicon substrate 1 in the area where the 2゜n layer 3 is to be formed, and then forming the P layer 2 with a predetermined spacing in the same way as in FIG. 1. ．． Each of the n layers 3 is formed by diffusion or the like. Although this structure can reduce the series resistance to direct current and high frequency signals, it complicates its manufacture, and the electrode lead 8 on the pocket-shaped hole 4 does not lose its flatness or is cut off at the large end. It is extremely unsuitable for mass production.
本発明の目的は上記の欠点を解消し、直列抵抗が小さく
量産効果の大きいＰＩＮダイオードを提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a PIN diode that has a small series resistance and is highly effective in mass production.
本発明のマイクロ波ダイオードは一導電型のシリコン基
板に所定の間隔を有する導電型の異なった２個の多結晶
シリコン領域を有し、一方の多結晶シリコン領域から一
導電型の不純物がシリコン基板の第１の領域に拡散され
、他方の多結晶シリコン領域から他の導電型を有する不
純物がシリコン基板の第２の領域に拡散され、これら第
１０領域と＠２の領域とは互いに対向して設けられてい
るものである。The microwave diode of the present invention has two polycrystalline silicon regions of different conductivity types separated by a predetermined distance on a silicon substrate of one conductivity type, and impurities of one conductivity type are distributed from one polycrystalline silicon region to the silicon substrate. An impurity having another conductivity type is diffused from the other polycrystalline silicon region into the second region of the silicon substrate, and these tenth region and @2 region face each other. It is provided.
以下、図面を参照して本発明のマイクロ波ダイオードと
してのＰＩＮダイオードの一実施例をよシ詳細に説明す
る。Hereinafter, one embodiment of a PIN diode as a microwave diode of the present invention will be described in detail with reference to the drawings.
第３図及び第４図は本発明による実施例のビームリード
形ＰＩＮダイオードの平面図と断面図を示す。これは高
比抵抗シリコン基板ｌｏ内の所定の部分に３〜５μ程度
の深さ穴を形成し、この穴をＡｓ等の不純物を含んだＮ
型多結晶シリコン１１によって充填してシリコン基板１
０表面と多結晶シリコン１１表面とを同じくする。又、
シリコン基板上のＮ型多結晶シリコン１】を有する穴と
対向する所定の位置に先と同様の穴を形成し、この穴に
Ｂ等の不純物を含んだＰ型多結晶シリコン１２を充填す
る。これら多結晶シリコンの充填は、シリコン基板１０
の所定部を陽極酸化によシ多孔質化し、ここに不純物を
拡散しても良い。その後、酸化膜、窒化膜等の絶縁膜１
３を形成し、所定の温度によって高抵抗シリコン基板１
０へ多結晶シリコン１１，１２に含まれるＡ ８１ Ｂ
等をそれぞれ拡散することによって高抵抗領域１４をは
さんでＮ 領域１５とＰ 領域１６が形成される。この
時、シリコン基板１０および多結晶シリコン１１゜１２
上には絶縁膜１３が形成されているが、このうち多結晶
シリコン１１．１２上の絶縁膜をエツチング等により選
択的に除去して電極窓１７ｔ−開ける。そしてこの電極
窓１７を通して蒸着、メッキ法等によシビームリード用
金属導体１８を形成し、ＰＩＮダイオードを形成する。3 and 4 show a plan view and a cross-sectional view of a beam-lead type PIN diode according to an embodiment of the present invention. This is done by forming a hole with a depth of about 3 to 5 μm in a predetermined part of the high resistivity silicon substrate lo, and then filling the hole with N
Silicon substrate 1 filled with mold polycrystalline silicon 11
The 0 surface and the polycrystalline silicon 11 surface are made the same. or,
A hole similar to that described above is formed at a predetermined position opposite to the hole containing N-type polycrystalline silicon 1 on the silicon substrate, and this hole is filled with P-type polycrystalline silicon 12 containing impurities such as B. These polycrystalline silicon fillings are performed on a silicon substrate 10.
A predetermined portion of the substrate may be made porous by anodic oxidation, and impurities may be diffused therein. After that, an insulating film 1 such as an oxide film or a nitride film is formed.
3 and high resistance silicon substrate 1 at a predetermined temperature.
A 81 B contained in polycrystalline silicon 11, 12 to 0
By diffusing these, an N region 15 and a P region 16 are formed with the high resistance region 14 in between. At this time, the silicon substrate 10 and the polycrystalline silicon 11°12
An insulating film 13 is formed thereon, and the insulating film on the polycrystalline silicon 11 and 12 is selectively removed by etching or the like to open an electrode window 17t. Then, a metal conductor 18 for a beam lead is formed through this electrode window 17 by vapor deposition, plating, or the like to form a PIN diode.
そしてダイオード機能を持った部分以外のシリコン基板
１ｏを化学エツチング等によシ除去しビームリード形Ｐ
ＩＮダイオードが形成される。Then, the silicon substrate 1o other than the part with the diode function is removed by chemical etching, etc., and the beam lead type P is removed.
An IN diode is formed.
このようにして形成した本実施例のＰＩＮダイオードに
よれば、不純物を含んだ多結晶シリコン１１゜１２が高
抵抗シリコン基板１０に設けられた所定ノ深すの穴に充
填され、この多結晶シリコン１１゜１２中に含まれる不
純物が拡散源となっているため・第１図に示す従来の実
施例のものにくらべよシ深い拡散層が得られる。このた
め、表面再結合５−
によるキャリアの寿命の減少を緩和し、ダイオードの直
列抵抗を減少することが出来る◎又、従来例では、直列
抵抗を減少させるために設けた第２図に示しだような穴
４が、本発明の実施例では多結晶シリコン１１・１２に
よって充填されているためリード１８の平面性を保つこ
とができ、量産性に優れたＰＩＮダイオードを製造でき
る。According to the PIN diode of this example formed in this way, the polycrystalline silicon 11° 12 containing impurities is filled into the hole of a predetermined depth provided in the high-resistance silicon substrate 10, and the polycrystalline silicon Since the impurities contained in the layers 11 and 12 serve as a diffusion source, a deeper diffusion layer can be obtained compared to the conventional embodiment shown in FIG. For this reason, it is possible to alleviate the decrease in carrier life due to surface recombination5- and reduce the series resistance of the diode. Since such holes 4 are filled with polycrystalline silicon 11 and 12 in the embodiment of the present invention, the flatness of the leads 18 can be maintained, and a PIN diode with excellent mass productivity can be manufactured.
第１図、第２図はそれぞれ従来のビームリード形ＰＩＮ
ダイオードを示す断面図、第３図および第４図は、本発
明の一実施例によるビームリード形ＰＩＮダイオードを
示す平面図および断面図である０
１．１０．１４・−・・・・高抵抗シリコン基板、２゜
１６・・・・・・Ｐ 層、３．１５・・・・・・Ｎ 層
、４・・・・・・穴部、６．１３・・・中絶縁膜、８．
１８・・・・・・金属リード、１１・・・・・・Ｎ型多
結晶シリコン、１２・・・・・・Ｐ型多結晶シリコン、
１７・・・・・・電極窓。
代理人 弁理士 内 原 晋Ｇ？ｂ
−ら −Figures 1 and 2 show conventional beam lead type PINs, respectively.
0 1.10.14 --- High resistance 0 1.10.14 --- High resistance Silicon substrate, 2゜16...P layer, 3.15...N layer, 4...hole, 6.13...middle insulating film, 8.
18...Metal lead, 11...N-type polycrystalline silicon, 12...P-type polycrystalline silicon,
17... Electrode window. Agent Patent Attorney Susumu Uchihara G? b - et al -
Claims (1)
所定の深さの２個の穴が形成され、この穴のそれぞれに
、異なった導電型を有する多結晶シリコン層が充填され
、これにょシ互に異なった導電型の低抵抗不純物領域が
上記高抵抗シリコンをはさんで形成されることを特徴と
するダイオード０A predetermined width is placed on a high-resistance silicon substrate of one conductivity type.
Two holes with a predetermined depth are formed, each of which is filled with a polycrystalline silicon layer having a different conductivity type, and a low-resistance impurity region of a different conductivity type is formed in the above-mentioned height. Diode 0 characterized by being formed by sandwiching resistive silicon
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14988583A JPS6041265A (en) | 1983-08-17 | 1983-08-17 | Diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14988583A JPS6041265A (en) | 1983-08-17 | 1983-08-17 | Diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6041265A true JPS6041265A (en) | 1985-03-04 |
Family
ID=15484762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14988583A Pending JPS6041265A (en) | 1983-08-17 | 1983-08-17 | Diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041265A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188282A (en) * | 1985-08-27 | 1987-08-17 | テイア−ルダブリユ− インコ−ポレ−テツド | Monolithic device and manufacture of the same |
| US5124066A (en) * | 1989-02-27 | 1992-06-23 | Lever Brothers Company, Division Of Conopco, Inc. | Storage-stable enzymatic liquid detergent composition |
| JPH0475259U (en) * | 1990-11-15 | 1992-06-30 |
-
1983
- 1983-08-17 JP JP14988583A patent/JPS6041265A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188282A (en) * | 1985-08-27 | 1987-08-17 | テイア−ルダブリユ− インコ−ポレ−テツド | Monolithic device and manufacture of the same |
| US5124066A (en) * | 1989-02-27 | 1992-06-23 | Lever Brothers Company, Division Of Conopco, Inc. | Storage-stable enzymatic liquid detergent composition |
| JPH0475259U (en) * | 1990-11-15 | 1992-06-30 |
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