JPS6075974A - Picture processor - Google Patents

Abstract

PURPOSE:To display a compound picture which is optimum for positioning and to facilitate the positioning of pictures by compounding object pictures in terms of division of position and displaying them. CONSTITUTION:The picture data of the 1st and 2nd memories 4 and 5 are read out by the addresses generated from column address generating circuits 2a and 2b and row address generating circuits 3a and 3b respectively. Memory read selecting circuits 6a and 6b inhibit or permit the output of the data read out of the memories 4 and 5. The circuits 6a and 6b divide the positions of subject pictures to be displayed on a screen by the outputs of column and row reading control circuits 11 and 12. These outputs are compounded by an OR circuit 7 and converted into analog signals by a D/A converting circuit 8 to be supplied to a CRT9.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an image processing device mainly used in an image diagnostic device d in the medical field, and in particular to a plurality of image processing devices used as pre-processing for image processing for diagnosis. This relates to alignment of images to be processed.

[Technical sequence of the invention and its problems] Cases in which image data is collected from multiple diagnostic imaging devices, or cases in which image data is collected from subjects (e.g., patients) at different times even with the same device, etc. In this case, slight differences in imaging conditions such as the imaging system cause deviations in the size of the image 1'tj and deviations in the position of the subject. therefore,
When performing such image processing on multiple images, such as inter-image calculations, it is necessary to align the positions and sizes of each image (hereinafter, for the sake of simplicity, "position and 1141 alignment" will simply be " (hereinafter referred to as "alignment").

Conventionally, when aligning such images, images are changed and displayed and compared, or images are superimposed by adding or subtracting between them, and this superimposed image is displayed. A method of aligning is used. However, when positioning is performed by switching images, if the image before switching is not memorized, there will be lag, and the switching of images may cause screen ``wobble''. The reason is simple.1. Yes. Also, if you want to overlap images,
I! When the L images are superimposed, the shading etc. of the images change, making them difficult to see, and there is also the problem that alignment is not easy.

OBJECT OF THE INVENTION An object of the present invention is to provide an image processing device that facilitates image alignment by displaying a composite image that is optimal for alignment.

[Summary of the Invention] The present invention, which achieves the above object, includes a reading means for reading image data from a plurality of image memories, and a display for prohibiting or permitting display of the image data of each image read by the reading means. a prohibition/permission means; an image display means for displaying a composite image based on the image data permitted by the means; The present invention is characterized in that it includes a control means for complementary display prohibition/permission of each target image on a column-by-column, one-row or multiple-row basis, and all combinations thereof.

[Embodiments of the invention] FIG. 1 shows the configuration of an embodiment of the present invention.

The display control circuit 1 generates a column address signal Sa, a row address signal Sb, and a horizontal/vertical synchronization signal Sc for displaying an image. The column address generation circuits 2a and 2b generate a column address for memory reading from a column address signal Sa, and the row address generation circuits 3a and 3b generate a column address for memory reading from a row address signal Sb. This is what causes responses. The first memory 4 and the second memory 5 are memories each storing an image to be processed. The memory read selection circuits 6a and 6b each have a first . It inhibits/enables the output of the read data Sd and Se read from the second memories 4 and 5, and in this case is a gate circuit consisting of an AND gate. The OR circuit 7 outputs data from the first memory 4 or the second memory 5 which is enabled to output and is provided from the memory read selection circuits 6a and 6b. D/A (digital)
The conversion circuit 8 converts the memory read data S [selected from the OR circuit 7 into an analog
Multiplier S (converts to +.CRT (cathode ray tube)
Reference numeral 9 displays image data using a video signal Sg and a horizontal/vertical synchronizing signal 3c. The inverting circuit 10 includes a first
The data output of either the second memory 4 or the second memory 5 is permitted, and the capability thereof is not permitted. The column readout circuit 11 outputs a column readout signal 3h in response to the column address signal 3a.

The row read control circuit 12 receives the row address signal 3
In response to signal b, the line read permission signal S1 is output. In this case, the row/column read permission circuit 13 is
consisting of column read and row read enable signals S
The OR of b and 3i is calculated and outputted as a memory read permission/disapproval signal.

Next, the operation of the above-described configuration will be explained.

Column address generation circuits 2a and 2b are generated by the column address signal 3a output from the display controller 1 to the roll circuit 1.
, the row addresses of the first memory 4 and the second memory 5 are generated. Further, the column address signal 3a is input to the column read controller 1 to the roll circuit 11, and the column read control circuit 11 outputs a column read permission signal sh. Similarly, the row addresses of the first memory 4 and the second memory 5 are generated from the row address generation circuits 3a and 3b according to the row address signal @S1 output from the display controller I to the roll circuit 1, and this row address Data is read from the first memory 4 and the second memory 5 according to the column address and the column address, and the read data is input to the memory read selection circuits 6a and 6b. Further, the row address signal sb is inputted to the row readout controller 1 to the roll circuit 12, and the row readout permission signal S1 is outputted from the row readout control circuit 12. Line read permission signal 3
i and the column read permission signal 311 are ORed by the row/column read permission circuit 13, and on the one hand are directly input to the memory read selection circuit 6b, and on the other hand are inputted directly to the memory read selection circuit 6b via the signal inversion circuit 10. It is input to the circuit 6a. In this way, the data read from the memory 4°; 5 is reversed, when the data output of the first memory 4 is selected (permitted), the data of the second memory 5 is not selected (prohibited), and vice versa. If X, (data output of memory 4 of 1 or not selected (jA, +1), then (
j, the data in the second memory 5 is selected (permitted). The output data of the memory read selection circuit (3a, 6b) is input to the D/A conversion circuit 8 as the selected memory read data 3f after being combined by the OR circuit 7, and the video signal S
is converted to The CRT 9 displays images using the video signal Sg and the horizontal/vertical synchronizing signal @SC output from the display r/control circuit 1. Reading of row readout control circuit 12 and column readout control circuit 11] By changing the control method,
Display can be performed using various display pattern methods.

A specific example of the image display method in this embodiment will be explained with reference to FIG.

Display image A is the image data (only) in the first memory 4
This is an image obtained when displaying 1 gi of display image.
Assume that B is the image obtained when displaying only the image data in the second memory 5 (note the direction of the hatching in both cases).Then, display image C (well, the row readout control circuit This is an image of this embodiment when the image data of the first memory 4 and the second memory 5 are displayed alternately for each row by 12.The display image @D is the image data of the column readout controllers 1 to 1.
The roll circuit 11 and the row readout controllers 1 to 12 alternately read the first memory 4 and the second memory 5 for each pixel.
This is an image of this embodiment when image data of That is. Display screen E is column read]
The image tK! of this embodiment when the image data of the first memo 4 and the second memo 5 are displayed alternately in the J-column fσ on the control circuit 11. There is r. In addition to this, by changing the switching timing and duty ratio of the target image between column readout and row readout, the strip-shaped, Display methods using various display patterns such as cutout image display are possible.

In other words, the target images are aligned and displayed on the display screen in 11 rows divided into f1'', so you can clearly see the mutual relationship between the two images, and each target image
Since the display gradation of the image is not hindered, the image speed and
It becomes possible to suitably and precisely match the positional relationship, etc.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented in various modifications without changing the gist thereof.

1. Effect of Light] According to the present defense, an image processing device is provided that can extremely easily perform image alignment (including thickness alignment), which is essential for pre-processing when processing multiple images. I can do something.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram for explaining image display according to the embodiment. 1...Display controller 1~roll circuit, 2a, 2b
... Column address generation circuit, 3a, 3b... Row address generation circuit, 4... First memory, 5... Second memory, (3a, ('3b... Memory read 'rll)
selection circuit, 7...OR circuit, 8...D/A conversion circuit,
9...CRT, 10...Inversion circuit, 11...Column readout controller 1 to roll circuit, 12...Row readout control circuit, 13...Row/column readout enable circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A readout means for reading image data from a plurality of image memories; a display prohibition/permission means for prohibiting/permitting display of image data of each image read by the means; It controls the image 1z1 display means for displaying a composite image based on image data, and the -jl display prohibition/'correction means, and controls the image display means for displaying a composite image based on image data, Every line or lines,
and a control means for controlling display of each target image by combining all of them as a unit (zero-complementary display prohibition and/or FF enable).