JPS6074815A - Clock generating circuit of switched capacitor circuit - Google Patents

Abstract

PURPOSE:To form a delay circuit in a small circuit scale by replacing a delay circuit using a train of inverters with a delay circuit using a capacitor. CONSTITUTION:A clock signal phi0 having a 50:50 time ratio between L and H levels is supplied to an input terminal. The signal phi0 is led to the input at one side of an NOR circuit 111 as well as to the input at one side of an NOR circuit 112 via an inverter circuit 121. The output of the circuit 111 is led to the input at the other side of the circuit 112 via a delay circuit 221 consisting of an inverter circuit 122 and a capacitor 211 as well as to output terminals 171 and 172 via an inverter circuit 124. Then clocks phi1 and phi2' are delivered from terminals 171 and 172. While the output of the circuit 112 is led to output terminals 181 and 182 via an inverter circuit. The clocks phi2 and phi2' are delivered from terminals 181 and 182. In such a constitution of a delay circuit using a capacitor, a large delay time is obtained with a small area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to Which the Invention Pertains] The present invention relates to the configuration of a clock generation circuit used in a Swiss-circuit capacitor filter.

[Description of prior art]

A switch capacitor filter is a filter composed of a switch, a capacitor, and an operational amplifier, and performs a filter operation by transmitting electric charge from one capacitor to another.

FIG. 1 shows a simple circuit example of a Swissito capacitor filter. In the same figure, 1 is an operational amplifier, 21 to 2
4 is a semiconductor switch controlled by clock φ1, 25~
28 is a semiconductor switch controlled by clock φ2, 31
-33 are capacitors. suisocito capacitor
In the operation of the filter, the clocks φ1 and φ2 are the second
It is necessary to have a section where both of the semiconductor switches 21 to 28 are at a low level, such as section T in the figure, in which all the semiconductor switches 21 to 28 are off.

As a conventional circuit for generating the clock shown in Fig. 2,
For example, the circuit shown in FIG. 3 or the circuit shown in FIG. 4 is used. The circuit shown in FIG. 3 is the NOR circuit 111.
．． 112, composed of impark circuits 121 to 125,
The circuit in Fig. 4 is an inverter circuit 121 to 125, NAN
It consists of D circuits 131, 132 and exclusive OR circuits 14, each of which has an inverter array 15 for creating a delay time corresponding to section T in FIG. In the circuits shown in FIGS. 3 and 4, a 50% duty clock φ0 is input to the terminal 16, clocks φ1 and il are input to the terminals 171 and '172, and clocks φ2 and φ2 are input to the terminals 181 and 182, respectively. Output. The time when the clocks φ1 and φ2 in FIG. 2 are simultaneously at a low level corresponds to the gate delay in the inverter array 15 in FIGS. 3 and 4.

The time when clocks φ1 and φ2 are low level is usually 50
Since about nanoseconds are required, this 50 nanosecond section can be achieved by using about 10 inverters with a gate delay time of 5 nanoseconds. However, with the development of LSI process technology, the gate delay time is becoming shorter.

For example, in a CMOS process using the 3 μm rule, the gate delay is 1 to 2 nanoseconds. Using this process, clocks φ1 and φ2 can be generated in the circuit shown in FIG. 3 or 4.
The disadvantage is that the number of inverters in the inverter array 15 becomes extremely large in order to make the inverter array 15.

[Purpose of the invention]

The present invention solves the above-mentioned drawbacks, and provides a clock generation circuit for a switched capacitor circuit having a structure capable of reducing the circuit scale when a switched capacitor circuit is manufactured by a micro-high-speed process. The purpose is to

[Key points of the invention]

The present invention is characterized in that, in a clock generation circuit that supplies a clock to a switching element of a Swiss capacitor circuit, a delay circuit using an inverter array conventionally used for the purpose of creating a time delay is replaced with a delay circuit using a capacitor. do.

[Explanation based on examples]

Embodiments of the present invention will be described below based on the drawings.

FIG. 5 is a block diagram showing a clock generation circuit according to a first embodiment of the present invention, in which the present invention is applied to the conventional circuit shown in FIG. In FIG. 5, a clock signal φ0 with a time ratio of low level and high level of 50:50 is input to the input terminal 16, and this signal φ0 is a NOR signal.
It is led to one input of the circuit 111 and also to one input of the NOR circuit 12 via the inverter circuit 121. The output of the NOR circuit 111 is guided to the other input of the NOR circuit 112 via a delay circuit 221 made up of an inverter circuit 122 and a capacitor 211, and also to an output terminal 171.17 via an inverter circuit 124.
2, and a clock ψ1.71 is output from these output terminals 171 and 172. In addition, the NOR circuit 112
The output of 1 is guided to the other input of the NOR circuit 11t via a delay circuit 222 consisting of an inverter circuit 123 and a capacitor 212, and is also guided to the output terminals IL and 182 via an inverter circuit 125. Clock φ2.12 is output from children 181 and 182.

As is clear from FIG. 5, in the first embodiment circuit according to the present invention, the inverter array 15 in the conventional circuit shown in FIG. 3 is replaced with a capacitor. In this way, by using a capacitor in the delay circuit, a large delay time can be realized with a small area. For example, 3μm rule commercial
In the OS process, by using capacitors 211 and 212 of approximately 2.59F, clock φ1,
It is possible to realize approximately 80 nanoseconds as the time when φ2 becomes low level at the same time. This first embodiment circuit can sufficiently reduce the area on the chip compared to the case where an inverter array is used.

FIG. 6 is a block diagram of the circuit according to the embodiment of the present invention shown in FIG. 2, and is an example in which the present invention is applied to the conventional circuit shown in FIG. In FIG. 6, the clock signal φ0 is guided to one input of the exclusive NOR circuit 14, and is also guided to the other input of the exclusive NOR circuit 14 via a delay circuit 223 consisting of an inverter circuit 122 and a capacitor 213, and to the NOR circuit 14.
It is led to one input of the ND circuit I31.132. The output of the exclusive NOR circuit 14 is the NAND circuit 13>, 1
32, this NAND circuit 1311
32 outputs are led to output terminals 171.172 and 181.182 via inverter circuits 12+12s, respectively. In this embodiment circuit of FIG. 2 as well, the delay circuit 22
3 can be significantly smaller than conventional inverter arrays, and the circuit scale can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, even when manufacturing a switched capacitor circuit 1/& using a CMOS process or the like, conventionally, a large number of inverters were required, resulting in a large circuit scale. It becomes possible to realize a delay circuit with a small circuit scale.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a Swissotito capacitor circuit. FIG. 2 is a timing diagram of clocks φ1 and φ2. FIGS. 3 and 4 are block diagrams of conventional clock generation circuits. FIG. 5 is a block diagram of the program of the circuit according to the first embodiment of the present invention. FIG. 6 is a block diagram of a circuit according to a second embodiment of the present invention. Ill, 112...NOR circuit, 121-124...
・Inverter circuit, 131.132...NAND circuit, 14...Exclusive NOR circuit, 211-213...
Capacitors, 221-223...Delay circuit. Patent applicant representative patent attorney Naotaka Ide 'l'I'("5.j

Claims (3)

[Claims] (1) A Swiss-chito capacitor circuit composed of a switching element, a capacitor, and an operational amplifier, and a clock generation circuit that supplies a clock signal for opening/closing control to the switching element of this Swiss-chito capacitor circuit are integrated into one integrated circuit. A clock generation circuit of a Swisso-chito capacitor circuit, characterized in that the time delay circuit included in the clock generation circuit is constituted by a circuit including a capacitor for time delay. (2) The clock generation circuit includes first and second N clock generation circuits. R circuit, first and second delay circuits each including an inverter circuit and a capacitor, and a signal having a time ratio of low level and high level of 50:50 is the first N circuit.
The inverted signal is input to the OR circuit and the second N
The output of the first NOR circuit is input to the second NOR circuit via the first delay circuit, and the output of the second NOR circuit is input to the first NOR circuit via the second delay circuit. 12. The clock generating circuit for a switched capacitor circuit according to claim 11, wherein the clock generating circuit is configured to obtain an output clock signal from the outputs of the first and second NOR circuits. (3) The clock generation circuit includes an exclusive NOR circuit, first and second NAND circuits, and a delay circuit including an inverter circuit and a capacitor, and the time ratio between low level and high level is 50 + 50. A signal is input to the exclusive NOR circuit, and passes through the delay circuit to the exclusive NOR circuit, the first NAND circuit, and the second NOR circuit.
The clock signal is input to an AND circuit, the output of the exclusive NOR circuit is input to the first and second NAND circuits, and an output clock signal is obtained from the outputs of the first and second NAND circuits. Claim No. (
A clock generation circuit for the switched capacitor circuit according to item 1).