JPS5830228A - Pulse distributing circuit - Google Patents

Abstract

PURPOSE:To supply a control signal whose delay time is set to a necessary minimum, to a switching element, by using an (n) stage shift register, and forming an on-control signal to an off-control signal by delaying it by a constant interval of time. CONSTITUTION:When an original signal is applied to an input point (a) of an (n) stage shift register 31, and a clock pulse having sufficiently high frequency and high accuracy, comparing with the original signal is applied to a point (g), the original signal is delayed by time td of (n) times of the clock period, and is outputted to an output terminal (b). A signal from the point (a) and a signal of the point (b), and signals which have inverted the signals from the point (a) and the point (b) by invertor gates 32, 33 are converted to AND signals by an AND gate 34 and an AND gate 35, respectively, and become outputs (e), (f) having a rise delay time td in which a rise time point of one signal is equal to (n) times of the clock pulse period, to a fall time point of the other signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides on-off control of switching elements in a circuit (for example, an inverter having switching elements such as puff transistors or thyristors) having a pair of switching elements connected in series to a power source. 6. One of the well-known inverters is a bridge type inverter as shown in FIG.

In such an inverter, two pairs of switch elements 1, 2, and 3 are connected in series to a DC power source 6.
It is necessary to apply an alternating current voltage to the load 5 by alternately turning on and off the voltages and 4.

By the way, in an actual switch element, the turn-off operation time of the switch is delayed with respect to the time point when a control signal (drive signal) applied to the element is given an turn-off command. Therefore, two switching elements 1 and 2. connected in series to the power supply 6. Or, if an ON control signal is immediately given to the other switch element in response to an OFF control signal for one of switch elements 3 and 4, a power supply short circuit may occur.For this reason, the 6-point waveform in Figure 3, point f. As shown in the waveform, it is necessary for the rising signal of one switching element to have a delay time td for the falling edge of the switching element's OFF control with respect to the multiple signals.However, it is necessary to delay the turning-on point of the switching element. Since this causes deterioration of the distortion rate of the output waveform of the inverter, the delay time when the control signal is turned on must be kept to the minimum necessary.Therefore, the on-control signal of the switch element as described above must be delayed and formed. The circuit is accurate and stable,
It is desired that the necessary minimum delay can be easily achieved.

A conventional example of such a control signal forming circuit for a switch element will be explained with reference to the circuit diagram in FIG. 2 and the waveform diagram in FIG. 3, thereby clarifying the object of the present invention.

In the circuit shown in FIG. 2, the original signal for driving the switch element is input to point α, and this signal is inverted by the inverter gate 11 to reach point b. The signal at point α and the signal at point b are delayed by a delay circuit consisting of a resistor 12 and a capacitor 13 or a resistor 14 and a capacitor 15, respectively.
The waveform will be at point and point d. The signals at point α and point 0 are input to the two-person gate 16, and the signals at points b and d are input to the two-person gate 17, and the respective AND signals are input to point e and f.
The output will be a point. The point at which the signal at point 0 or point d exceeds the threshold level of the two gates 16 and 17 is the point at which the signal at point α or point b exceeds the threshold level. It slows down like a waveform.

Therefore, the signal at point e is the signal at point α, and the signal at point f is b
The rising point of the signal at point is delayed by the time td. On the other hand, the falling points of the signals at points e and f are equal to the falling points of the signals at points α and b, respectively. Therefore, between the signals at points e and f, when one signal rises (here, this is the control signal that turns on the switch element), the other signal falls (
This is here a control signal for turning off the switch element) and has a delay time td.

However, the control signal forming circuit shown in FIG. 2 has the following drawbacks.

b) Variation in the time constant of the integrating circuit and ant gate 1
Due to variations in the threshold levels of 6 and 17, variations in delay time td occur between each delay circuit,
Furthermore, the delay time td varies as the time constant changes due to temperature and aging.

As a result, the delay time td must be set to be long with some margin. As a result, the distortion rate of the output voltage of the inverter may deteriorate.

Incidentally, among the above-mentioned drawbacks, (a) can be removed by using a comparator as shown in FIG. That is, in FIG. 4, each of the elements 11 to 17 is the same as that in FIG. 2, and between each delay circuit and the AND gate, there are comparators 23 and 24, and a comparator v-I! Return resistance 2o
, 21. Variable resistor 2 for threshold level adjustment
Adjustment may be made possible by intervening a comparator circuit consisting of 8 and 29. However, the shortcomings of (mouth) cannot be resolved.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse distribution circuit which can eliminate the above-mentioned disadvantages and can accurately and stably supply a control signal with a minimum delay time to a switching element.

According to the present invention, this purpose is to delay an on control signal for a certain period of time with respect to an off control signal using an n-stage shift register in a pulse distribution circuit that controls on/off of a plurality of switching elements connected in series with a power supply. This is achieved by forming the

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a circuit diagram of a control signal forming circuit of the present invention using an n-stage shift register 31, and FIG. 6 is a waveform diagram showing waveforms at each point in FIG.

Clock input terminal 31 of n-stage shift register 31
A clock signal is input from point g to -1.

An original signal for control is input to the input terminal 31-2,
The input point α of this original signal is input to the two-person AND gate 35 via an AND gate 31 and an inverter game;
An output terminal 31-3 of the stage shift register 31 is connected to an AND gate 35 via an AND gate 34 and an inverter gate 33. The output terminals of AND gates 34 and 35 are connected to points e and f, respectively, which provide control signals to the switch elements.

Next, to explain the operation, here, the original signal (
When a highly accurate clock pulse with a frequency sufficiently higher than that of this original signal is applied to point g, the output terminal 31-3 of the n-stage shift register 31 outputs the original signal as a clock. The output is delayed by a time td which is n times the period (dot waveform in Figure 6). The signal from the α point and the shifted signals from the output terminal 31-3 Z>2 (the α point waveform and the b point waveform in FIG. 6, respectively) are processed by the AND gate 34, and the signals from the α point and the b point are The signals obtained by inverting the signals (the waveforms at point C and the waveform at point d in Fig. 6, respectively) are applied to the AND gate 35.
It is converted into an AND signal.

As a result, the output signals of 34 and 35 (waveforms at point e and waveform at point f in Fig. 6) are such that one signal rises at multiple times and the other signal falls at multiple times. On the other hand, it has a rise delay time td equal to n times the clock pulse period.

These e point and f point signals are applied, for example, to the gate of the thyristor (or base of the transistor) constituting the switch element 1.4 in FIG.
．． When a point f signal is applied to the gate of the thyristor (or the pace of the transistor) that makes up the bow, either switch elements 1 or 2 or switch elements 3 and 4 are always turned off due to the delay time td. Therefore, there will be no power supply short circuit.

Note that the present invention may also be applied to a control signal generation circuit that delays the falling edge signal by inverting the e-point and f-point signals of the above embodiment using an inverter gate.

As described above, the present invention uses an n-stage shift register without using resistors or capacitors to delay the ON control signal for a certain period of time with respect to the OFF control signal of the switch element, so the delay time td is pulse frequency f
Determined only by c (Hz) and the number of shift stages n of the n-stage shift register, td = n / f c (seconds), and is subject to temperature changes and aging.

In principle, it can be assumed that no variation in delay time occurs due to variations in the integral constant or the like.

Therefore, it is possible to keep the delay time of the ON control signal highly accurate and stable, and reduce it to the minimum necessary value using a simple circuit.

Furthermore, even if it is necessary to use a large number of control signal forming circuits, by supplying a common clock signal to each n-stage shift register, the variation in delay time of all control signals can be reduced to a negligible level. There are also things.

[Brief explanation of drawings]

Figure 1 is a conceptual circuit diagram of a bridge type inverter, Figure 2 is a conventional control signal formation circuit diagram, Figure 3 is a waveform diagram at each point of the circuit in Figure 2, and Figure 4 is a conventional control using a comparator. A signal forming circuit diagram, FIG. 5 is a circuit diagram showing an embodiment of the present invention, and FIG. 6 is a waveform diagram at each point in the circuit diagram of FIG. 1.2, 3.4...Switch element 5...
・Load 6...DC power supply 1]...--Inverter 12, 14...Resistor 13, 1
5...Capacity 16, 17...2 person gate 28, 29...Variable resistance
20, 21...Feedback resistors 22, 23...
...Comparator 31...N-stage shift register 3x-z, 3z-2...Input terminal 31-3...Output terminal 32, 33...
...Inverter gate 34', 35...And gate applicant Fuji Electric Manufacturing Co., Ltd. Fang 1 Figure 2 Figure 6 Figure 4

Claims (1)

[Claims] In order to alternately turn on and off a pair of switch elements connected in series to a power supply, control pulses for each switch element are formed from a pulse signal that is inverted at each desired switching point of the switch element. In the pulse distribution circuit, a shift register is provided which receives the pulse signal and outputs a pulse signal whose rise and fall are delayed by a fixed time determined by the clock frequency and the number of stages with respect to the pulse signal. , due to the logical combination of pulse signals on the input side and output side of this shift register, there is a time difference corresponding to the above-mentioned fixed time between the time when one switch element is commanded to turn off and the time when the other switch element is commanded to turn on. Pulse distribution circuit control characterized in that it forms control pulses for the individual switching elements as they occur in each case.