JPS6074806A - Constant current bias generating circuit - Google Patents

Constant current bias generating circuit

Info

Publication number
JPS6074806A
JPS6074806A JP58182322A JP18232283A JPS6074806A JP S6074806 A JPS6074806 A JP S6074806A JP 58182322 A JP58182322 A JP 58182322A JP 18232283 A JP18232283 A JP 18232283A JP S6074806 A JPS6074806 A JP S6074806A
Authority
JP
Japan
Prior art keywords
transistor
emitter
resistor
collector
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58182322A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sano
芳昭 佐野
Eiji Nishimori
英二 西森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58182322A priority Critical patent/JPS6074806A/en
Publication of JPS6074806A publication Critical patent/JPS6074806A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To avoid the effect of the variation of the power supply voltage by constituting a constant current bias generating circuit with four transistors and two resistances and to secure the specific conditions for the relation between the emitter areas of said transistors. CONSTITUTION:A constant current bias generating circuit consists of transistors (TR) Q1-Q4 and resistances R1 and R2. The TRs Q1-Q4 have the same emitter area and the TRQ4 has its emitter area which is (n) times as much as those of other TRQs. It is decided that the current value of the R1 and TRs Q1 and Q2 is equal to I1 and the current value of TRs Q3 and Q4 and the R2 is equal to I0 respectively as long as the current amplification factor of each TR is satisfactorily large. The relation shown by an equation I is obtained since the saturated current value is proportional to the emitter area, where (k), T and (q) show the Boltzmann constant, absolute temperature and electronic charge respectively. In the equation I the output current I0 has no relation with the output current I1. Therefore it is possible to obtain a stable constant output current I0 regardless of the power supply voltage and the resistance R1.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、定電流バイアス発生回路に関し、特に、電源
電圧変動の影響を受けない定電、流バイアス発生回路に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a constant current bias generation circuit, and more particularly to a constant current, current bias generation circuit that is not affected by fluctuations in power supply voltage.

〔従来技術と問題点〕[Prior art and problems]

従来、定電流バイアス発生回路として、第1図に示され
るような回路が用いられている。第4図の回路は、トラ
ンジスタQs 、Q2および抵抗R。
Conventionally, a circuit as shown in FIG. 1 has been used as a constant current bias generating circuit. The circuit of FIG. 4 includes transistors Qs, Q2 and a resistor R.

から構成される。第1図の回路において、トランジスタ
Q2のエミッタ面積がトランジスタQsのエミッタ面積
のn倍に設計されているとすると、Io=n■、トなる
。トランジスタQlを通る電流I tは、電源電圧V。
It consists of In the circuit of FIG. 1, if the emitter area of the transistor Q2 is designed to be n times the emitter area of the transistor Qs, then Io=n■. The current It through transistor Ql is equal to the supply voltage V.

c、トランジスタQ1のベースエミッタ’IEEVBH
お、よび抵抗Rユにより次式のように決定される。
c, base emitter of transistor Q1 'IEEVBH
It is determined by the following equation by R, R, and resistance R.

11=(vCC−vBEl)/R1 従って、出力電流I。は、負荷と無関係に次式1式% ) ところで、この電流値は電源電圧によシ変動するため、
電源電圧の変動に影響を受けるという問題がある。
11=(vCC-vBEl)/R1 Therefore, the output current I. is the following equation (1), regardless of the load.By the way, this current value varies depending on the power supply voltage, so
There is a problem in that it is affected by fluctuations in power supply voltage.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、前記の従来技術の問題点にかんがみ、
電源電圧の変動による影響を受けない定電流バイアス発
生回路を提供することにある。
In view of the problems of the prior art described above, the object of the present invention is to
An object of the present invention is to provide a constant current bias generation circuit that is not affected by fluctuations in power supply voltage.

〔発明の構成〕 前記の目的を達成するために、本発明においては、正側
電源と負側電源の間に直列に接続される第1の抵抗、第
1および第2のトランジスタ、および、電流出力端と該
負側電源の間に直列に接続される第2の抵抗、第3およ
び第4のトランジスタを有する定電流バイアス発生回路
であって、該第1の抵抗は該正側電源と該第1のトラン
ジスタのコレクタの間に接続され、該第1のトランジス
タのペースがそのコレクタに接続され、該第1のトラン
ジスタのエミッタが該第2のトランジスタのコレクタに
接続され、該第2のトランジスタのエミッタは該負側電
源に接続され、該第3のトランジスタのコレクタは該電
流出力端に接続され、該第3のトランジスタのペースは
該第1のトランジスタのペースに接続され、該第3のト
ランジスタのエミッタは直接または該第2の抵抗を介し
て該第4のトランジスタのコレクタに接続され、該第4
のトランジスタのペースは該第2のトランジスタのコレ
クタに接続され、該第2のトランジスタのペースは該第
4のトランジスタのコレクタに接続され、該第4のトラ
ンジスタのエミッタは該第2の抵抗を介してまたは直接
に該負側電源に接続され、該第1および第2のトランジ
スタのエミッタ面積および該第3または第4のトランジ
スタのいずれか一方のエミッタ面積は同一であシ、該第
3または第4のトランジスタの他方のエミッタ面積は他
のトランジスタのn倍であることを特徴とする定電流バ
イアス発生回路が提供される。
[Structure of the Invention] In order to achieve the above object, the present invention includes a first resistor, first and second transistors, and a current A constant current bias generation circuit having a second resistor, third and fourth transistors connected in series between an output terminal and the negative power supply, the first resistor connected to the positive power supply and the a first transistor connected between the collectors of the first transistor, the first transistor's pace being connected to the collector thereof, and the emitter of the first transistor being connected to the collector of the second transistor; an emitter of the third transistor is connected to the negative power supply, a collector of the third transistor is connected to the current output terminal, a pace of the third transistor is connected to a pace of the first transistor, and a collector of the third transistor is connected to the current output terminal; The emitter of the transistor is connected directly or through the second resistor to the collector of the fourth transistor, and the fourth
The pace of the transistor is connected to the collector of the second transistor, the pace of the second transistor is connected to the collector of the fourth transistor, and the emitter of the fourth transistor is connected to the collector of the second transistor. or directly connected to the negative power supply, the emitter areas of the first and second transistors and the emitter area of either the third or fourth transistor are the same; There is provided a constant current bias generation circuit characterized in that the emitter area of the other transistor of No. 4 is n times larger than that of the other transistors.

〔発明の実施例〕[Embodiments of the invention]

本発明による宇電流ノ々イアス発生回路を図面によυ以
下に説明する。
The current noise generating circuit according to the present invention will be explained below with reference to the drawings.

第2図は、本発明の第1の実施例としての定電流バイア
ス発生回路が示される。第2図の定電流バイアス発生回
路は、トランジスタQ1 、Q2 。
FIG. 2 shows a constant current bias generation circuit as a first embodiment of the present invention. The constant current bias generation circuit shown in FIG. 2 includes transistors Q1 and Q2.

Qs lQ4および抵抗RI I R2から構成される
It consists of Qs lQ4 and resistor RI I R2.

トランジスタQ1 *Qt +Qaのエミッタ面積は同
一であり、トランジスタQ4のエミッタ面積は他のトラ
ンジスタのn倍となるように形成、される。
The emitter areas of the transistors Q1 *Qt +Qa are the same, and the emitter area of the transistor Q4 is formed to be n times larger than that of the other transistors.

各トランジスタの電流増幅率が充分大であるとすると、
抵抗R1、)ランジスタQt−Qsを流れる電流値は工
、に等しく、トランジスタQ t + Q4 a抵抗R
2を流れる電流値は工。に等しいと見なせる。各トラン
ジスタのペース・エミッタ電圧VBmciで表わされる
。ここで、l(:yl?ルツマン定数、T:絶対温度、
q:電子の電荷、工、l:飽和電、流である。トランジ
スタQ、のコレクタ電位vcは、VC”v111C1+
vBE4+IOR2=vBI2+vBE5であり、飽和
電流値はエミッタ面積に比例するのが成立つ。従って、  kT I o−R2,tn n が得られる。この出力電流IOは、11 とは無関係で
あり、従って、電源電圧VCCおよび抵抗R8に影響さ
れない安定な定電流出力IOが得られる。
Assuming that the current amplification factor of each transistor is large enough,
Resistor R1,) The current value flowing through transistor Qt-Qs is equal to
The value of the current flowing through 2 is . can be considered to be equal to It is represented by the pace emitter voltage VBmci of each transistor. Here, l(: yl? Lutzmann constant, T: absolute temperature,
q: electron charge, q; l: saturation current, current. The collector potential VC of the transistor Q is VC"v111C1+
vBE4+IOR2=vBI2+vBE5, and it holds true that the saturation current value is proportional to the emitter area. Therefore, kT I o-R2,tn n is obtained. This output current IO is independent of 11, and therefore a stable constant current output IO that is not affected by power supply voltage VCC and resistor R8 is obtained.

第3図は、本発明の第2の実施例としての定電流バイア
ス発生回路を示す。第3図の回路は、トランジスタQ2
のエミ、り面積が他のトランゾスタの1倍であシ、抵抗
R3がトランジスタQ2のエミッタとトランジスタQ4
のコレクタの間に接伏されている点が第2図の回路と異
なる。第3図の回路の出力電流は、第2図の場合と同一
であり、電源電圧の影響を受けない。
FIG. 3 shows a constant current bias generation circuit as a second embodiment of the present invention. The circuit of Fig. 3 consists of transistor Q2
The area of the emitter of transistor Q2 is twice that of other transistors, and resistor R3 is connected to the emitter of transistor Q2 and transistor Q4.
The circuit differs from the circuit shown in FIG. 2 in that it is connected between the collectors of the circuit. The output current of the circuit of FIG. 3 is the same as that of FIG. 2 and is not affected by the power supply voltage.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電源電圧変動による影響を受けない安
定な定電流バイアス発生回路が提供され得る。
According to the present invention, a stable constant current bias generation circuit that is not affected by power supply voltage fluctuations can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の定電流バイアス発生回路の回路図、 第2図は、本発明の第1の実施例としての定電流バイア
ス発生回路の回路図、 第3図は、本発明の第2の実施例としての定電流バイア
ス発生回路の回路図である。 (符号の説明) Ql +Q* *Qa #Q4 :)ランジスタ〜R1
、R2:抵抗。
FIG. 1 is a circuit diagram of a conventional constant current bias generation circuit, FIG. 2 is a circuit diagram of a constant current bias generation circuit according to a first embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional constant current bias generation circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of a constant current bias generation circuit as an example of FIG. (Explanation of symbols) Ql +Q* *Qa #Q4:) Ranister ~R1
, R2: resistance.

Claims (1)

【特許請求の範囲】[Claims] 正側電源と負側電源の間に直列に接続される第1の抵抗
、第1および第2のトランジスタ、および、電流出力端
と該負側電源の間に直列に接続される第2の抵抗、第3
および第4のトランジスタを有する定電流バイアス発生
回路であって、該第1の抵抗は該正側電源と該第1のト
ランジスタのコレクタの間に接続され、該第1のトラン
ジスタのペースがそのコレクタに接続され、該第1のト
ランジスタのエミッタが該第2のトランジスタのコレク
タに接続され、該第2のトランジスタのエミッタは該負
側電源に接続され、該第3のトランジスタのコレクタは
該電流出力端に接続され、該第3のトランジスタのペー
スは該第1のトランジスタのペースに接続され、該第3
のトランジスタのエミッタは直接捷たけ該第2の抵抗を
介して該第4のトランジスタのコレクタに接続され、該
第4のトランジスタのペースは該第2のトランジスタの
コレクタに接続され、該第2のトランジスタのペースは
該第4のトランジスタのコレクタKW続され、該第4の
トランジスタのエミッタは該第2の抵抗を介してまたは
直接に該負側電源に接続され、該第1および第2のトラ
ンジスタのエミッタ面積および該第3または第4のトラ
ンジスタのいずれか一方のエミッタ面積は同一であり、
該第3または第4のトランジスタの他方のエミッタ面積
は他のトランジスタのn倍であることを特徴とする定電
流バイアス発生回路。
A first resistor, first and second transistors connected in series between a positive power source and a negative power source, and a second resistor connected in series between a current output terminal and the negative power source. , 3rd
and a fourth transistor, the first resistor is connected between the positive power supply and the collector of the first transistor, and the first resistor is connected to the collector of the first transistor. , the emitter of the first transistor is connected to the collector of the second transistor, the emitter of the second transistor is connected to the negative power supply, and the collector of the third transistor is connected to the current output. the third transistor pace is connected to the first transistor pace, and the third transistor pace is connected to the first transistor pace;
The emitter of the transistor is directly connected to the collector of the fourth transistor through the second resistor, the base of the fourth transistor is connected to the collector of the second transistor, and the emitter of the fourth transistor is connected directly to the collector of the fourth transistor through the second resistor. The pace of the transistor is connected to the collector of the fourth transistor, the emitter of the fourth transistor is connected to the negative power supply via the second resistor or directly, and the emitter of the fourth transistor is connected to the negative power supply through the second resistor. and the emitter area of either the third or fourth transistor are the same,
A constant current bias generation circuit characterized in that the emitter area of the other of the third or fourth transistor is n times larger than that of the other transistor.
JP58182322A 1983-09-30 1983-09-30 Constant current bias generating circuit Pending JPS6074806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58182322A JPS6074806A (en) 1983-09-30 1983-09-30 Constant current bias generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58182322A JPS6074806A (en) 1983-09-30 1983-09-30 Constant current bias generating circuit

Publications (1)

Publication Number Publication Date
JPS6074806A true JPS6074806A (en) 1985-04-27

Family

ID=16116278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58182322A Pending JPS6074806A (en) 1983-09-30 1983-09-30 Constant current bias generating circuit

Country Status (1)

Country Link
JP (1) JPS6074806A (en)

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