JPS62117019A - Constant current generating circuit - Google Patents
Constant current generating circuitInfo
- Publication number
- JPS62117019A JPS62117019A JP60256953A JP25695385A JPS62117019A JP S62117019 A JPS62117019 A JP S62117019A JP 60256953 A JP60256953 A JP 60256953A JP 25695385 A JP25695385 A JP 25695385A JP S62117019 A JPS62117019 A JP S62117019A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- constant current
- current
- emitter
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Electrical Variables (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、α精度な定（１ｔが１８を発生させることが
可能な定量Ｉ′５流発生回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a constant I'5 current generation circuit capable of generating an α-accurate constant (1t = 18).
従来の技術
従来、この種の定電流発生回路は第２図の回路図に示さ
れる構成のものがよく知られている。第２図中、トラン
ジスタＱ＋ 、Ｑ２ 、ＱＳ 、Ｑｂ および抵抗Ｒ１
は、バンドギャップ方式と呼ばれる定電流発生回路部で
あり、これに対して、ダイオード接続のトランジスタＱ
ｓ 、 Ｑａおよび抵抗Ｒ２＋ Ｒ５でなる起動回路部
が結合され、トランジスタＱ５． Ｑｂと電流ξラー結
合されたトランジスタＱ７ を通じて、負荷抵抗Ｒ，に
定電流が供給されるという構成である。ここで、トラン
ジスタＱ１と同Ｑ２、ならびにトランジスタＱ５とＱｂ
は、それぞれ、異なる電流密度で動作するように、エミ
ッタ面積が異なる構成である。2. Description of the Related Art Conventionally, this type of constant current generating circuit has a well-known configuration as shown in the circuit diagram of FIG. In Figure 2, transistors Q+, Q2, QS, Qb and resistor R1
is a constant current generation circuit section called a bandgap type, and on the other hand, a diode-connected transistor Q
s, Qa and a starting circuit section consisting of resistors R2+R5 are coupled and transistors Q5. The configuration is such that a constant current is supplied to the load resistor R through the transistor Q7 which is connected to Qb by a current ξ. Here, transistors Q1 and Q2, and transistors Q5 and Qb
are each configured with different emitter areas to operate at different current densities.
発明が解決しようとする問題点
このような従来の構成では、電源電圧（’／ｃｃ ）が
変動すると、ＱｌとＱ２．ＱＳとＱｂの各々のトランジ
スタのコレクタ・工ｉ、タ間電圧（”／（４） が太
きく異なるだめ、定電流値が電源電圧により大きく変動
する。このことを詳１，２ぐ１賛明する３、今、各トラ
ンジスタの電流増幅率（ｈｙｉ）を無限大とし、コｌ／
クタ電流Ｉ（Ｈ４（ｉ＝１〜７）とすると（１）〜（６
）式の関係が成り立つ。Problems to be Solved by the Invention In such a conventional configuration, when the power supply voltage ('/cc) fluctuates, Ql and Q2 . Since the voltages between the collectors and the terminals of the QS and Qb transistors are greatly different, the constant current value varies greatly depending on the power supply voltage. 3. Now, let the current amplification factor (hyi) of each transistor be infinite, and
If the vector current I (H4 (i = 1 to 7) is
) holds true.
但シ、ｌ５ｉ（ｉ−１〜７）はベース・エミッタ間通バ
イアス時の飽和電流
Ｖｃ ｔｉ （ｉ−１〜７）Ｈコｖりｐ ０工εツタ間
電圧
ＶｈＬ （ｉ＝１〜７） はアーリー電圧Ｖａｇｉ（
１＝１〜７）はベース・工ｉツタ間電圧
にはボルツマン定数
ｑは電子の電荷
Ｔは接合温度
Ｒ１（ｉ＝１〜３）は各抵抗値、である。However, l5i (i-1 to 7) is the saturation current Vc ti (i-1 to 7) during base-emitter bias voltage VhL (i = 1 to 7) is the early voltage Vagi (
1=1 to 7) is the voltage between the base and the terminal i, the Boltzmann constant q is the electron charge T, and the junction temperature R1 (i=1 to 3) is each resistance value.
／！ｎ＝ Ｉｓ＋／Ｉｓｚ ＋ ｖｉｔ ＝ＶＡ２＃
ｐ＝Ｉｓｓ／Ｉｓ６＋ ’／１ｓ＝Ｖｉ６また・工引
＝ＩＣ５ＩＣ２＝工Ｃ６だからＶｃｃ＞Ｉｃ２Ｒ＋＞Ｉ
ａ＋Ｒ２とすると
上記（６）式の関係からもわかるように、定電流値は電
源電圧の変動に弱いという問題があった。/! n=Is+/Isz+vit=VA2#
p=Iss/Is6+ '/1s=Vi6 Also, engineering = IC5IC2=engine C6, so Vcc>Ic2R+>I
If a+R2 is used, there is a problem in that the constant current value is sensitive to fluctuations in the power supply voltage, as can be seen from the relationship in equation (6) above.
本発明はこのような問題点を解決するもので、電源電圧
が変動しても定電流値が変化しない定電流発生回路を提
供することを目的とするものであるＯ
問題点を解決するための手段
本発明は、要約するに、第１．第２の各電流源を能動負
荷とし、異なる電流密度で動作する電流ミラー対の第１
．第２のトランジスタをそなえ、前記第１のトランジス
タのコレクタと前記第１゜゛第２のトランジスタの共通
ベースとの間に、前記第１．第２の各電流源に電流ミラ
ー結合された第３のトランジスタおよび抵抗でなる起動
回路によって駆動される第４のトランジスタを結合させ
た構成である。The present invention solves these problems, and aims to provide a constant current generating circuit whose constant current value does not change even if the power supply voltage fluctuates. Means The present invention can be summarized as follows: 1. The first of the current mirror pairs operates at different current densities, with each second current source as an active load.
．． a second transistor between the collector of the first transistor and the common base of the first and second transistors; In this configuration, each second current source is coupled with a third transistor that is current mirror-coupled and a fourth transistor that is driven by a starting circuit that includes a resistor.
作用
この構成により、電源電圧の変動に対して安定な定電流
値の定電流発生回路が実現される。Effect: With this configuration, a constant current generating circuit with a constant current value that is stable against fluctuations in power supply voltage is realized.
実姉例
第１図は本発明の一実施例による定電流発生回路の回路
図であり、第１図において、トランジスタＱ＋ｓ及びＱ
１６．抵抗Ｒ１２は起動回路として働き、トランジスタ
Ｑ＋ｓ及びＱ１６により、トランジスタＱ１４のエミッ
タ・コレクタ間電圧ｖａｘ１ａは、はぼベース・工εツ
タ間電圧ｖｉｘｅ４になり、トランジスタＱ＋３ ＋
Ｑ１４のアーリー効果を打ち消す働きをする。Actual Example Fig. 1 is a circuit diagram of a constant current generating circuit according to an embodiment of the present invention. In Fig. 1, transistors Q+s and Q
16. The resistor R12 works as a starting circuit, and the emitter-collector voltage vax1a of the transistor Q14 becomes the voltage vixe4 between the base and the base due to the transistors Q+s and Q16, and the transistor Q+3 +
It works to negate the early effect of Q14.
また、トランジスタ（ｈ＋のエミッタ・コレクタ間電圧
ＶＱＩ＋もトランジスタＱ１２のエミッタ・コレクタ間
電圧ＶＣＨ２とほぼ等しくなり、アーリー効果を打ち消
している。Furthermore, the emitter-collector voltage VQI+ of the transistor (h+) is approximately equal to the emitter-collector voltage VCH2 of the transistor Q12, canceling out the Early effect.
以上のようにして発生した定電流はトランジスタＱ＋ｙ
の様にミラー結合しているトランジスタにより負荷ＲＬ
に供給される。The constant current generated as above is the transistor Q+y
The load RL is
is supplied to
この時、基準の電流源の電流値は、電源電圧の変動を受
けないだめ、トランジスタＱ１７のアーリー効果分だけ
である。At this time, the current value of the reference current source is only affected by the Early effect of the transistor Q17 since it is not subject to fluctuations in the power supply voltage.
この構成により、第１図において、トランジスタＱ１４
のエミッタ・コレクタ間電圧ｖａｚ１ａは次式％式％
””’８１１１４
となり、トランジスタＱ＋５のエミッタ・コレクタ間電
圧”ＣＨ！ｌとほぼ等しくなる。With this configuration, in FIG.
The emitter-collector voltage vaz1a is expressed by the following formula % ``'''81114, which is approximately equal to the emitter-collector voltage ``CH!l'' of the transistor Q+5.
また、トランジスタＱ＋＋のエミッタ９コレクタ間電圧
ＶＣＩＮ及びトランジスタ（ｈ２のエミッタ・コレクタ
間電圧ＶＣＫ＋２は次式の様になる。Further, the emitter-collector voltage VCIN of the transistor Q++ and the emitter-collector voltage VCK+2 of the transistor (h2) are expressed by the following equation.
Ｖｃ冨＋＋ ＝ ｖｃｃ ｖｃ凰１４＝Ｖｃｃ Ｖ
ｍｘ＋ａ
ＶＣＴＬ＋２ ” ｖｃａ −”ＣＩ＋３−ＩＨ２Ｒ１
１＝ Ｖｃｃ −ＶＢ冨１３． Ｉｃ＋２Ｒ＋
＋＜（Ｖｃｃし、たが〕て、トランジスタＱ１１．Ｑ１
２のエミッタ・コレクタ間電圧がほぼ等しくなる。Vc wealth++ = vcc vc凰14=Vcc V
mx+a VCTL+2 ”vca-”CI+3-IH2R1
1=Vcc-VB 13. Ic+2R+
+<(Vcc, but), transistor Q11.Q1
The emitter-collector voltages of the two transistors become almost equal.
そのため、アーリー効果の影響がなくなり、電源電圧Ｖ
ＣＣが変動しても、定電流値が変動しない定電流源発生
回路が得られる。Therefore, the influence of the Early effect disappears, and the power supply voltage V
A constant current source generation circuit in which the constant current value does not vary even if CC varies can be obtained.
発明の効果
以」二のように本発明によれば、少ない素子数で電源電
圧変動に強く、高精度な電流が発生するという効果が得
られる。Advantages of the Invention As described in (2), the present invention has the advantage of being resistant to power supply voltage fluctuations and generating highly accurate current with a small number of elements.
Claims (2)
流密度で動作する電流ミラー対の第１、第２のトランジ
スタをそなえ、前記第１のトランジスタのコレクタと前
記第１、第２のトランジスタの共通ベースとの間に、前
記第１、第２の各電流源に電流ミラー結合された第３の
トランジスタおよび抵抗でなる起動回路によって駆動さ
れる第４のトランジスタを結合させたことを特徴とする
定電流発生回路。(1) The first and second current sources are used as active loads, and the first and second transistors of a current mirror pair that operate at different current densities are provided, and the collector of the first transistor and the first and second transistors are connected to each other. A fourth transistor driven by a starting circuit comprising a resistor and a third transistor current-mirror-coupled to each of the first and second current sources is coupled between the common base of the two transistors. A constant current generation circuit featuring:
特許請求の範囲第１項記載の定電流発生回路。(2) The constant current generating circuit according to claim 1, wherein the fourth transistor is a PNP transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60256953A JPS62117019A (en) | 1985-11-15 | 1985-11-15 | Constant current generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60256953A JPS62117019A (en) | 1985-11-15 | 1985-11-15 | Constant current generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62117019A true JPS62117019A (en) | 1987-05-28 |
Family
ID=17299654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60256953A Pending JPS62117019A (en) | 1985-11-15 | 1985-11-15 | Constant current generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62117019A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01166607A (en) * | 1987-12-22 | 1989-06-30 | Mitsubishi Electric Corp | Constant current generating circuit |
| US4937515A (en) * | 1988-08-29 | 1990-06-26 | Kabushiki Kaisha Toshiba | Low supply voltage current mirror circuit |
| WO2016030993A1 (en) * | 2014-08-27 | 2016-03-03 | 三菱電機株式会社 | Biasing device and wakeup circuit |
-
1985
- 1985-11-15 JP JP60256953A patent/JPS62117019A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01166607A (en) * | 1987-12-22 | 1989-06-30 | Mitsubishi Electric Corp | Constant current generating circuit |
| US4937515A (en) * | 1988-08-29 | 1990-06-26 | Kabushiki Kaisha Toshiba | Low supply voltage current mirror circuit |
| WO2016030993A1 (en) * | 2014-08-27 | 2016-03-03 | 三菱電機株式会社 | Biasing device and wakeup circuit |
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