JPS6074660A - Three-dimensional logic circuit - Google Patents

Abstract

PURPOSE:To enable to have equal plane areas on a chip, and to remove the phenomenon of latch-up action a structural defect of a CMOS device by a method wherein a logic element is prepared on a wafer in three-dimensions. CONSTITUTION:The gate 1 of an N-MOST is connected to the gate 20 of a P- MOST by means of a poly Si wiring 21 and turns to the input of this CMOS inverter. When a positive voltage is impressed on the wiring serving as the input, with VCC as the positive potential; the gate poly Si 1 of the N-MOS connected to the wiring turns to a positive voltage, and the gate poly Si 20 of the P-MOST to a positive voltage. The turning of the gate poly Si of the N-MOST to a positive voltage induces electrons in the neighborhood of the surface of a P<-> substrate 6 contacting the gate oxide film 2 of a P<-> region sandwiched between P<-> diffused layers 4 and 5 placed between N<+> diffused layers 4 and 5. As a result, the channel activates, and the N-MOST turns ON. At the same time, when the gate poly Si of the P-MOST turns to a positive voltage, the P-channel does not activate and turns OFF.

Description

[Detailed description of the invention] The present invention relates to logic circuits.

In conventional 0MO8 logic elements, logic elements are formed on a wafer two-dimensionally, or multi-planarly. Single-channel three-man power NOR with N-channel MO8 structure shown in Figure 1
As can be seen by comparing the circuit with the CMO8 structure three-man power NOR circuit shown in Figure 2, the 0MO8)9 register (hereinafter referred to as C-MO8T) is an N-channel type MO8) run lister (hereinafter referred to as N-MO8T). ) and P-channel type M
O8) Since it is based on complementary operation with the run lister (hereinafter referred to as P-MO8T), first of all, N-MO8'
Compared to a single-channel MO8 integrated circuit configured with I' or P-MOS T, an integrated circuit with a C-MO8T configuration requires less C-MOS when forming the same circuit on a chip.
Since the MO8T configuration has a larger number of F transistors, it has the disadvantage that the chip area becomes larger.

Second, there are structural defects specific to CMOS devices. FIG. 3 shows a schematic cross-sectional view of a CMOS device. Third
In the figure, 2.3.6.7.10 is a channel stopper in the octopus or P+ region produced by ion implantation for preventing parasitic channels.

81.82, 83.84 are bipolar transistors that are parasitic to this CMOS device.The cross-sectional schematic diagram of this CMOS device is overlaid with a schematic diagram to show what kind of configuration bipolar transistors are produced. This is what is illustrated. In FIG. 3, an NPN transistor S2 has a P well 4 as a base, an N type silicon substrate 25 as an emitter, and an N+ diffusion layer as a collector 5. The P+ diffusion layer 1 is used as an emitter, and the P well 4 is used as a collector. The other 83.84 are similarly damned.

Furthermore, Fig. 4 shows that the parasitic bipolar transistor in Fig. 3 is the main factor that causes the two-touch-up operation phenomenon.In order to simply explain the principle, a circuit is created using the parasitic bipolar transistor in Fig. 3. It is a circuit diagram. Fourth
In the figure, VCC is a positive voltage power supply. If a negative voltage that is lower than the ground voltage of the circuit is input to input terminal 1, 17
．． r8→16. r7→5. S2→3. r i→1. A current flows through the input terminal, and the current causes 5.82
2, VCC-+12. r
4-+13. r 5-+5.82-+3. ri-
+l, through the input terminal, the collector current IC of 5.82
IJ flows and a potential difference occurs between terminals 12 and r4,
This potential difference is 6, the base and emitter voltage of S3 VBEs
When 2.83 is exceeded, the transistor 6.83 is also turned on, and 2. V
CC→6. S3→15, r 6-417. r 8→
3. Connect GND 6.83 Collector current ICEj
flows. Under the above power conditions, 1. Even if the negative voltage input to the input terminal is cut off and becomes the ground voltage of this circuit, 1.
Because the voltage drop continues to occur in 748, this 17.
Since the transistor j9.5.82 remains on due to the voltage drop of r8, the collector current ICE of 5.82
I continues to flow, so 6. Since the transistor S3 also remains on, the collector current ICEI of 6.83 also continues to flow, and the current continues to flow unless the power is turned off once.
A latch-up operation phenomenon occurs due to structural defects specific to S devices.

The present invention increases the planar area efficiency on a chip, which has traditionally been considered a drawback of CMOS devices, by creating logic elements three-dimensionally, that is, three-dimensionally, on a wafer. In contrast, when configuring the same circuit function with a CMOS device, it is possible to have the same planar area on the chip, and further,
It is an object of the present invention to provide a CMOS device having a structure that makes it possible to eliminate the latch-up phenomenon, which is a structural defect of CMOS devices.

FIG. 5 shows a schematic cross-sectional view of a CMOS device for explaining the present invention in detail. As shown in Figure 5, N-channel MO
8) Having a run lister, the N-channel MOS transistor 8) is perpendicularly opposed to the surface of the semiconductor chip on which the run lister is formed, and is structurally separated from the N-channel MOS transistor by an insulating film. P channel MO
B): a P-type MO8 conductor having an It conductor, in which the gate of the N-channel MOS transistor and the gate of the P-channel MO8) run-lister form the N-channel MO8) run-lister; MO8) It is characterized in that it is sandwiched between the N-type M08 semiconductor in which a run lister is formed.

By creating the three-dimensional structure described above), it is possible to generate the same 5-circuit function on a silicon chip with a 0MO8 configuration while occupying approximately the same area on a semiconductor chip as a single channel MO8 configuration. do. Furthermore, due to the three-dimensional structure described above and the presence of the insulating film sandwiched between the N-channel MO8) runlister and the P-channel MO8) runlister, the parasitic bipolar transistor as explained in the conventional example described above is prevented. This makes it possible to eliminate the latch-up phenomenon, which has been regarded as a structural defect of conventional CMOS devices.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a schematic cross-sectional view of a CMOS device explaining the present invention in detail.

The CMOS inverter of this example is N-channel MO8)
A runlister portion is formed on a P-type substrate, and the N-channel M
O8) An N-channel MO8) has wiring for the transistor on the transistor, and further has an insulating film to cover the upper part of the N-channel MO8) transistor, and an N-type transistor that is epitaxially grown on the insulating film. It has a silicon layer, a P-channel MOS transistor formed on the N-type silicon layer, and a wiring for a P-channel MOS transistor on the N-type silicon layer.

In FIG. 5, gate 1 of N-MO8T and gate 1 of P-MO8T
The gate 20 of the 8T is connected to a polysilicon wiring 21 and serves as an input to the present CMOS inverter. Now, VCC is a positive voltage, and when a positive voltage is applied to the input polysilicon wiring 21, the N-MO8 connected to the polysilicon wiring 21
The gate polysilicon 1 of T has a positive voltage, and the gate polysilicon 20 of P-MO8T has a positive voltage. Since the gate polysilicon 1 of N-MO8T becomes a positive voltage, N+
Electrons are induced near the surface of the P-substrate 6 in contact with the gate oxide film 2 in the P- region sandwiched between the P-diffusion layers 4 and 5, and as a result, the channel is activated. is turned on, and N-MO8T goes into the on state. At the same time P-MO8'
117) When the gate polysilicon 20 becomes a positive voltage, the P channel is inactivated and turned off. Therefore, the aluminum wiring 10 connected to GND! connected to the diffusion layer 4;
Since the output aluminum wire #J12 is connected to the N+ diffusion layer 5, the GND level changes from aluminum wire 10 → N+ diffusion layer 4 → activated channel → relay diffusion layer 5 → aluminum wire 12 (excluding 8. Passes through the P+ diffusion layer.), and the GND level is transmitted to the output via the above path. Conversely, when the GND level is applied to the polysilicon wiring 21, the P-MO8T is turned on, the N-MO8T is turned off, and so on.
is connected to the P+ diffusion layer 7 and serves as an output aluminum wiring 12
is connected to the P+ diffusion layer 8, so the positive level of vCC is transmitted to the output. Above all, with this structure, CMO
An S inverter is configured.

As is clear from this example, the present CMOS device configured on a chip has a smaller planar surface area on the chip than conventional CMOS devices, and also has an N-
By structurally separating and arranging the MO8T and the P-MO8T, the ratte-up phenomenon has been successfully eliminated.

As explained above, the present invention provides a CMOS device with a three-dimensional structure so that a 0MOS device can have the same planar area on a chip as compared to a single channel MOS device when configuring the same circuit function. Furthermore, the three-dimensional structure and N-MO8T and P-M
The structural isolation and placement of O8T has the effect of eliminating the latch-up behavior phenomenon caused by structural defects in conventional CMOS devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a three-man power NOR gate circuit having an N-MO8'l' configuration. FIG. 2 is a diagram showing a three-man power NOR gate circuit having a C-biO8T configuration. FIG. 3 shows a schematic cross-sectional view of a conventional CMOS device. fi, 1, 8.9...P diffusion layer, 5.12...N+ diffusion layer, 2,7...
・N+ channel stopper, 3, 6, 10...P
+ Channel stopper, 4...P well, 25.
...N-type silicon/substrate, 18...Silicon oxide film, 19...Gate silicon oxide 9- film, 20...Gate polysilicon, 17...・
...Aluminum wiring, 16...Input terminal. Figure 4 is a circuit diagram using the parasitic bipolar transistor shown in Figure 3 in order to explain the operating principle that causes the launch-up operation phenomenon mainly caused by the parasitic bipolar transistor shown in Figure 3. be. FIG. 5 is a schematic cross-sectional view of a CMOS device for explaining the present invention in detail. 1...N-MO8T gate polysilicon, 2
・・・・・・N-MO8T gate oxide film, 20...
...P-MO8T gate polysilicon, 3...
・・P-MOS T gate oxide film, 4, 5...
...N+ diffusion layer, 7, 8...P+ diffusion layer, 6.
...Pi silicon substrate, 9...Nu epitaxial growth layer, 10.14...Aluminum wiring connected to GND (ground), 11.13...
Aluminum wiring connected to VCC (power supply), 12...
...Aluminum arrangement for output, 15.16...N
+ channel stopper, 17.18...P+ channel stopper, 19...insulating film, 21...
...Polysilicon wiring that serves as input.

Claims (1)

[Claims] It has an N-channel MOS transistor and a P-channel MOS transistor that are structurally separated by an insulating film, and the N
Both the gate of the channel MOS transistor and the gate of the P-channel MO8) run lister are connected to the N-channel MO8)? A three-dimensional logic circuit, characterized in that it is sandwiched between a P-type semiconductor region in which a run lister is formed and an N-type semiconductor region in which a P-channel MO8) run lister is formed.