JPS59193065A - Transistor device - Google Patents
Transistor deviceInfo
- Publication number
- JPS59193065A JPS59193065A JP6719983A JP6719983A JPS59193065A JP S59193065 A JPS59193065 A JP S59193065A JP 6719983 A JP6719983 A JP 6719983A JP 6719983 A JP6719983 A JP 6719983A JP S59193065 A JPS59193065 A JP S59193065A
- Authority
- JP
- Japan
- Prior art keywords
- well
- electrode
- wells
- substrate
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims description 13
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明はトランジスタ装置に関するものである。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a transistor device.
ＭＯ３Ｉ−ランジスクは、動作を安定させるため、基板
の電位を一定（適音は接地電位）にしておく必要がある
。このため、単一のＭＯ３Ｉ−ランジスタで精度よく交
流電源を制御するのは困難である。交流電源を精度よく
制御するためには、複数のトランジスタを用いて回路を
構成する必要があるが、このようにすると装置が大形化
するという問題を生じる。In order to stabilize the operation of the MO3I-Landisk, it is necessary to keep the potential of the board constant (appropriately the ground potential). Therefore, it is difficult to accurately control the AC power supply with a single MO3I transistor. In order to accurately control an AC power source, it is necessary to configure a circuit using a plurality of transistors, but this poses a problem of increasing the size of the device.
この発明は、装置を大形化することなく交流電源の制御
をしうるトランジスタ装置の提供をその目的とする。An object of the present invention is to provide a transistor device that can control an AC power source without increasing the size of the device.
この発明は、Ｎ形およびＰ形のいずれかの基板内に他方
の形のウェルが複数個形成され、それぞれのウェル内に
基板と同し形の第１の不純物領域が形成され、さらにこ
の第１の不純物領域内にそのウェルと同じ形の第２の不
純物領域が形成されており、各ウェルの上の基板面部分
において、そのウェルと接続する第１の電極が形成され
ているとともに、この第１の電極に隣接する部分に、そ
のウェルおよびそのウェル内の第１．第２の不純物領域
にまたがるようにゲート酸化膜を介してゲート電極が形
成されており、さらにこのゲート電極に隣接する部分に
、一端が他のウェルの第１および第２の不純物領域にま
たがって接続され中間部が基板に接続されている共通電
極の他端がそのウェルの第１および第２の不純物領域に
またがって接続された状態で形成されており、そのウェ
ルのゲート電極と他のウェルのゲート電極とが共通ゲー
ト電極化されていることを特徴とするトランジスタ装置
をその要旨とするものである。In the present invention, a plurality of wells of the other type are formed in either an N type or a P type substrate, a first impurity region having the same shape as the substrate is formed in each well, and a first impurity region having the same shape as the substrate is formed in each well. A second impurity region having the same shape as the well is formed in the first impurity region, and a first electrode connected to the well is formed on the substrate surface portion above each well. The well and the first electrode in the well are adjacent to the first electrode. A gate electrode is formed through a gate oxide film so as to span the second impurity region, and further, in a portion adjacent to the gate electrode, one end thereof spans the first and second impurity regions of another well. The other end of the common electrode, whose intermediate portion is connected to the substrate, is formed in a state where it is connected across the first and second impurity regions of the well, and the gate electrode of the well and the other well are connected to each other. The gist of the invention is a transistor device characterized in that the gate electrodes of the transistor and the gate electrode of the transistor are made into a common gate electrode.
すなわち、このようにすることにより、装置を大形化す
ることなく交流電源の制御をしうるようになる。That is, by doing so, it becomes possible to control the AC power supply without increasing the size of the device.
つぎに、この発明を実施例にもとづいて詳しく説明する
。Next, the present invention will be explained in detail based on examples.
第１図はこの発明の一実施例のＮチャネルＭＯＳトラン
ジスタ装置の構成図である。図において、１はＰ形基板
、２，２′はＮ−ウェル、３．３′はそれらのウェル２
，２′内に形成されたＰ領域、４，４′はそのＰ領域３
．３′内に形成されたＮ＋領領域ある。これらのウェル
２，２′上の基板面部分には、そのウェル２，２′と接
続する電極５，５′が形成され、またそのウェル２，２
′のＰ領域３．３′およびＮ＋領域４．４′ならびにそ
のウェル２，２′にまたがるゲート電極６．６′がゲー
ト酸化膜を介して形成され、さらに共通電極７の端部が
次のように取付けられている。すなわち、共通電極７は
、一端が他方のウェル２’ （２）のＰ領域３’
（３）およびＮ′″領域４′ （４）にまたがって接続
され、中間部が基板１に接続されており、他端がそのウ
ェル２ （２’ ）のＰ領域３（３Ｍおよびに領域４（
４’）４こまたがって接続されている。上記ゲート電極
６゜６′は、リート線８によって共通電極化されてシｓ
る。６０はその共通端子である。FIG. 1 is a block diagram of an N-channel MOS transistor device according to an embodiment of the present invention. In the figure, 1 is a P-type substrate, 2, 2' are N-wells, and 3.3' are their wells 2.
, 2', and 4, 4' are the P regions 3
．． There is an N+ region formed within 3'. Electrodes 5, 5' are formed on the substrate surface portions above these wells 2, 2', and are connected to the wells 2, 2'.
A gate electrode 6.6' spanning the P region 3.3' and N+ region 4.4' of ' and the wells 2 and 2' is formed via a gate oxide film, and the end of the common electrode 7 is It is installed as follows. That is, the common electrode 7 has one end connected to the P region 3' of the other well 2' (2).
(3) and N''' region 4' (4), the middle part is connected to substrate 1, and the other end is connected to P region 3 (3M and region 4 of well 2 (2')). (
4') Connected across 4 pieces. The gate electrodes 6゜6' are made into a common electrode by the lead wire 8, and the system
Ru. 60 is its common terminal.
この発明にかかるトランジスタ装置でＧよ、鎖糸泉で囲
まれた部分Ａ、Ｂかそれぞれ独立したＭＯＳ１−ランジ
スタとなっており、それぞれのトランジスタＡ、Ｂは、
図にみるように絶縁分離されて（、Ｓる。なお、電極５
，５′の下側のウェル２，２′の部分には、その電極５
，５′とシリコンとの）氏抗を低下させるためのＮ１拡
散層１０．１０’力く形成されている。上記のＮ−ウェ
ル２．２’ｌよ、それぞれのＭＯ５＋−ランジスタＡ、
Ｂのドレイン部分となっている。上記ＭＯ３）ランジス
タへ。In the transistor device according to the present invention, the parts A and B surrounded by the chain string spring are each independent MOS transistors, and each transistor A and B are as follows:
As shown in the figure, the electrode 5
, 5' in the wells 2, 2' below the electrodes 5'.
, 5' and silicon) are strongly formed to reduce the resistance between them. The above N-well 2.2'l, each MO5+- transistor A,
This is the drain part of B. MO3) above to the transistor.
Ｂにおいて、１１．１１’がチャネル形成部分となり、
４，４′がソース部分となる。この部分４．４′は、Ｐ
領域（拡散層）３．３’に埋め込んで形成することによ
り、ドレイン部分２．２′力）らの分離がなされている
。なお、上記共通電極７は、その中間部において基板１
と接続されてし）るが、これはドレイン２，２′のＮ−
Ｐｉとの逆ノ＼イアス状恕をつくるためである。In B, 11.11' becomes the channel forming part,
4 and 4' become the source part. This part 4.4' is P
The drain portion 2.2' is separated by being buried in the region (diffusion layer) 3.3'. Note that the common electrode 7 is connected to the substrate 1 at its intermediate portion.
This is connected to N- of drains 2 and 2'.
This is to create an inverse relationship with Pi.
このように、このＮチャネルＭＯ３Ｉ−ランジスタ装置
は、分離されたＮ−ウェル２，２′中に独立してつくら
れたＭＯＳ）ランジスタＡ、Ｂを築積して構成されてい
る。この回路図を第２図に示す。図において、６０は共
通ゲー１へ電極端子、５０はトランジスタＡにおける電
極５の端子、５０′はトランジスタＢにおける電極５′
の端子である。なお、ＰチャネルＭＯ３）ランジスタの
構成では、第１図のＰとＮとが入れ換わることとなるこ
のＮチャネルＭＯ５＋−ランジスク装置の動作について
説明する。オフ状態（デー１−電極６，６′に印加され
る電圧がトランジスタのしきい値以下の場合）であって
、電極５に電圧が印加され、電極５′が接地状態の場合
には、トランジスタΔ、Ｂはオフとなっている。共通電
極７はほは接地レベルであるから１．トランジスタＡと
基板１ （Ｐ形部分）とは逆バイアスされ電流は流れな
い。In this way, this N-channel MO3I-transistor device is constructed by stacking independently fabricated MOS transistors A and B in separated N-wells 2 and 2'. This circuit diagram is shown in FIG. In the figure, 60 is the electrode terminal to the common gate 1, 50 is the terminal of electrode 5 in transistor A, and 50' is the electrode terminal 5' in transistor B.
This is the terminal. In the configuration of the P-channel MO3) transistor, the operation of this N-channel MO5+- transistor device in which P and N in FIG. 1 are interchanged will be described. In the off state (when the voltage applied to Day 1 - electrodes 6 and 6' is below the threshold of the transistor), when voltage is applied to electrode 5 and electrode 5' is grounded, the transistor Δ and B are off. Since the common electrode 7 is at ground level, 1. Transistor A and substrate 1 (P-type part) are reverse biased and no current flows.
この回路は左右対称であるから電極５と電極５′とが逆
転しても同様である。このオフ状態から、デー１−電極
６，６′にしきい値以上の電圧が印加されると、オン状
態となり電流が、電極５−→トランジスタへ−共通電極
７−トランジスタＢの経路で流れるようになる。この場
合、接地側のトランジスタＢは、ＰＮ接合が順バイアス
の状態になるため、チャネル部分１１′だけでなく、Ｐ
Ｎ接合からも電流が流れ、抵抗成分が低下する。Since this circuit is symmetrical, the same effect will occur even if the electrodes 5 and 5' are reversed. From this OFF state, when a voltage higher than the threshold voltage is applied to D1-electrodes 6 and 6', the state becomes ON and current flows through the path of electrode 5->transistor-common electrode 7-transistor B. Become. In this case, since the PN junction of the ground side transistor B is in a forward bias state, not only the channel portion 11' but also the P
Current also flows from the N junction, reducing the resistance component.
つぎに、上記ＮチャネルＭｏｓ＋−ランジスク装置の製
造の一例について説明する。すなわぢ、第３図に示すよ
うに、Ｎ−／Ｐ＋シリコンエピタキシャルウェハ１にＰ
形分離拡散層１ａを形成する。１ｂはＳｉＯ□膜である
。ついで、第４図に示すように、チャネルおよびヘース
となるＰ層３．３′を形成し、さらに第５図に示すよう
に、ソースおよびコンタクト部分のＮ” ！４．４’
、１０゜１０′を形成する。そして、ゲート酸化膜、コ
ンタクト窓を形成して電極５．５’、６．６’、７を形
成することにより第６図に示すようなＮチ４・ネルＭＯ
３）ランジスク装置が得られる。Next, an example of manufacturing the above-mentioned N-channel Mos+-range disk device will be described. In other words, as shown in FIG.
A shape separation diffusion layer 1a is formed. 1b is a SiO□ film. Next, as shown in FIG. 4, a P layer 3.3' serving as a channel and a heath is formed, and as shown in FIG.
, 10°10'. Then, by forming a gate oxide film, a contact window, and forming electrodes 5.5', 6.6', and 7, an N-channel 4-channel MO as shown in FIG.
3) A Landisk device is obtained.
この発明のトランジスタ装置は、以」二のように構成さ
れるため、１チツプ上にそれぞれが分離さｈたｍ数のＭ
ｏ３）ランジスタを形成でき、それらの接続によって安
定した交流制御が可能になる。この場合、装置の大形化
の問題は生しない。Since the transistor device of the present invention is constructed as described below, there are M transistors each having h m number of transistors separated on one chip.
o3) Transistors can be formed, and stable AC control can be achieved by connecting them. In this case, the problem of increasing the size of the device does not arise.
第１図はこの発明の一実施例の構成図、第２図はその回
路図、第３図ないしは第６図は同しくその製造説明図で
ある。
１・・・基板 ２．２′・・・ウェル ３，３′・・・
Ｐ？ｉＪｊ域 ４．４′・・・Ｎ“領域 ５．５′・・
・電極 ６゜６′・・・ゲート電極 ７・・・共通電極
９・・・共通ゲート電極 １０．１０’・・・Ｎ＋領
領域Ａ、Ｂ・・・Ｉ−ランジスタ部分
代理人 弁理士 松 本 武 彦FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram thereof, and FIGS. 3 to 6 are illustrations for explaining its manufacture. 1...Substrate 2.2'...Well 3,3'...
P? iJj area 4.4'...N" area 5.5'...
・Electrode 6゜6'...Gate electrode 7...Common electrode 9...Common gate electrode 10.10'...N+ territory A, B...I- transistor partial agent Patent attorney Matsumoto Takehiko
Claims (1)
ウェルが複数個形成され、それぞれのウェル内に基板と
同じ形の第１の不純物領域が形成され、さらにこの第１
の不純物領域内にそのウェルと同じ形の第２の不純物領
域が形成されており、各ウェルの上の基板面部分におい
て、そのウェルと接続する第１の電極が形成されている
とともに、この第１の電極に隣接する部分に、そのウェ
ルおよびそのウェル内の第１．第２の不純物領域にまた
がるようにゲート酸化膜を介してゲート電極が形成され
ており、さらにこのゲート電極に隣接する部分に、一端
が他のウェルの第１および第２の不純物領域にまたがっ
て接続され中間部が基板に接続されている共通電極の他
端がそのウェルの第１および第２の不純物領域にまたが
って接続された状態で形成されており、そのウェルのゲ
ート電極と他のウェルのゲート電極とが共通ゲート電極
化されていることを特徴とするトランジスタ装置。(1) A plurality of wells of the other type are formed in either an N-type or P-type substrate, a first impurity region having the same shape as the substrate is formed in each well, and
A second impurity region having the same shape as the well is formed in the impurity region of the well, and a first electrode connected to the well is formed on the substrate surface portion above each well. 1 adjacent to the first electrode in that well and the first electrode in that well. A gate electrode is formed through a gate oxide film so as to span the second impurity region, and further, in a portion adjacent to the gate electrode, one end thereof spans the first and second impurity regions of another well. The other end of the common electrode, whose intermediate portion is connected to the substrate, is formed in a state where it is connected across the first and second impurity regions of the well, and the gate electrode of the well and the other well are connected to each other. A transistor device characterized in that the gate electrode and the gate electrode are made into a common gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6719983A JPS59193065A (en) | 1983-04-15 | 1983-04-15 | Transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6719983A JPS59193065A (en) | 1983-04-15 | 1983-04-15 | Transistor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59193065A true JPS59193065A (en) | 1984-11-01 |
| JPH041509B2 JPH041509B2 (en) | 1992-01-13 |
Family
ID=13337992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6719983A Granted JPS59193065A (en) | 1983-04-15 | 1983-04-15 | Transistor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59193065A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021182211A1 (en) * | 2020-03-13 | 2021-09-16 | ローム株式会社 | Semiconductor device and method for manufacturing same |
-
1983
- 1983-04-15 JP JP6719983A patent/JPS59193065A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021182211A1 (en) * | 2020-03-13 | 2021-09-16 | ローム株式会社 | Semiconductor device and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH041509B2 (en) | 1992-01-13 |
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