JPS6074560A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the formation of a parasitic transistor in the lateral direction, and to improve latch-up withstanding voltage by forming a groove to a semiconductor substrate, burying an insulator and terminating a p-n junction in a well. CONSTITUTION:An Si3N4 film 11, an MoSi2 film 12 and a photo-resist film 13 are formed to an n type silicon semiconductor substrate 1, a groove 12A is formed through selective etching, and the Si3N4 film 11 is etched to shape a groove 11A. B ions are implanted to form a p type well 2. The substrate 1 is etched to form fine grooves around the p type well 2, SiO2, etc. are buried, and insulator films 14 are shaped. Each impurity diffusion region, contact region and electrode are formed, thus forming CMOS structure consisting of an n channel side transistor QN and a p channel side transistor QP. The current amplification factor of a p-n-p transistor constituted by the p type well 2, the n type substrate 1 and a p<+> type impurity diffusion region 8 in the lateral direction remarkably lowers, and latch-up withstanding voltage is improved.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method suitable for manufacturing a semiconductor device having a structure effective in preventing latch-up.

Prior Art and Problems FIG. 1 is a cutaway side view of the main parts of a typical conventional CMO3 semiconductor device.

In the figure, 1 is an n-type semiconductor substrate, 2 is a p-type well, and 3
is the gate electrode of the n-channel transistor, 4 and 5 are n+ type impurity diffusion regions for forming the n-channel transistor, 6 is the p+ type ground contact region, 7 is the gate electrode of the p-channel transistor, and 8 and 9 are the gate electrodes of the p-channel transistor. A p + -type impurity diffusion region for forming a p-channel transistor, 10 indicate an n1-type power supply contact region, and VDtl indicate a positive power supply level, respectively.

It is well known that in such a CMO5 semiconductor device, a parasitic bipolar transistor is formed and is likely to exhibit a latch-up phenomenon due to the silica effect.

That is, an npn transistor is formed vertically by an n+ type impurity diffusion region 4, a p type well 2, and an n type semiconductor substrate 1, and a horizontal structure is formed by a p type well 2, an n type semiconductor substrate 1, and a p+ type impurity diffusion region 8. It is a pnp) transistor configured in the direction.

FIG. 2 shows the structure of the parasitic bipolar transistor in terms of an equivalent circuit.

In the figure, Ql is a parasitic npn transistor, Q2 is a parasitic pnp transistor, R1, R2, R3, R4, R
5 indicates the internal resistance of each part.

These transistors Ql and Q2 are normally off, but if for some reason, for example, a noise current flows into the base of the transistor Q1, the transistor Q1 is turned on. Since the amplification factor of this transistor Q1 is quite large, it draws a large current in the on state, causing a potential drop in the resistor R5, and as a result, the transistor Q1 draws a large current.
Current also flows to the base of 2, turning it on. and,
The on state of these transistors Q1 and Q2 is maintained even if the cause of turning them on is resolved, that is, the noise current disappears, and the state is so-called a launch-up state. It goes without saying that it does not function as a CMO3 semiconductor device. Incidentally, such a latch amplifier phenomenon occurs more easily as the semiconductor device becomes finer.

Therefore, in order to suppress the launch amplifier phenomenon of such a CMO3 semiconductor device, a structure was proposed in which the pn junction part around the p-type well was replaced with oxide isolation (see Japanese Patent Application Laid-Open No. 1983-1993). (See Publication No. 151574).

However, the method for forming the oxide isolation in this prior art is to make the silicon semiconductor substrate porous by anodizing, and then thermally oxidize that portion, and the width of the isolation is approximately 10 mm. [μm], which is unsuitable for current high-density integrated circuits.

By the way, technology related to narrow insulator isolation is currently being actively researched and developed, but even if this technology is applied to insulator isolation around wells in CMO3 semiconductor devices, , the technology must be fully compatible with the manufacturing process of CMO3 semiconductor devices.

OBJECTS OF THE INVENTION Based on the above technical background, the present invention provides a method for forming insulator isolation by self-alignment during the manufacturing process of a CMO3 semiconductor device.
Further, it is possible to improve the latch-up breakdown voltage of the obtained CMO3 semiconductor device.

Structure of the Invention In the method for manufacturing a semiconductor device of the present invention, the surface of a semiconductor substrate is covered with a film that can be etched by reactive ions, and further covered with a photoresist, so that a portion of the semiconductor substrate where a well of a conductivity type opposite to that of the semiconductor substrate is to be formed is formed. An opening is formed in the photoresist, the film around the opening is removed by reactive ion etching, and an opposite conductivity type impurity is introduced into a region of the semiconductor substrate defined by the opening to form a well. form,
A trench is formed in the semiconductor substrate at the same position as the removed portion of the film, and an insulating material is buried in the trench so that the pn junction in the well is terminated with the insulating material. The formation of physical isolation is performed by self-alignment, and for example, apart from the vertical npn transistor shown in FIG. 1, the horizontal pnp transistor is formed blocked by the insulating film filling the trench. Therefore, the launch-up withstand voltage is dramatically improved.

Embodiment of the Invention FIGS. 3 to 8 are cross-sectional side views of essential parts of a CMO8 semiconductor device at key points in the process for explaining the case of manufacturing an embodiment of the present invention. This will be explained with reference to each figure. Note that the same parts as those described with reference to FIGS. 1 and 2 are indicated by the same symbols.

Refer to Figure 3 ■ Chemical vapor deposition (CV) is applied to the n-type silicon semiconductor substrate 1.
By applying silicon nitride (Si3N4 method)
) The film 11 is formed to a thickness of about 1500 mm.

■ By applying the magnetron sputtering method, the molybdenum silicide (MOSi2) film 12 is formed to a thickness of 30 mm.
Form to about 00 (persons).

■ A photoresist film 13 is formed by applying photolithography technology, and an opening 13A for forming a well is formed by applying predetermined processing such as baking, exposure, and development, and then buttering it. do.

As a result, a portion of the MoSi2 film 12 is exposed within the opening 13A.

■ The entire parallel plate type reactive ion beam
Placed in an etching device and used cc1 as an etchant.
Reactive ion beam etching is performed using a 4+O2 gas mixture.

Normally, when this type of etching is performed, the portions not covered with the photoresist film I3 will be etched, but the partial pressure ratio of 02 in the etchant mixture gas should be adjusted to about 60 to 70%. When the etching is increased relative to , etching is performed only along the edges of the photoresist film 13, and a narrow groove 12A is formed. The width of this narrow groove 12A is less than 1 [μm] pl, which is extremely fine. For details regarding this technology, please refer to the patent application 1986-20.
Issue 9173 or magazine “Semiconductor World”
(October 1983, pages 49 to 62)
Please refer to the following.

See Figure 4 ■ Applying reactive ion etching method, M.

A groove lIA similar to the groove 12A is formed by masking the S12 film 12 and etching the Si3N+1*11.

■ After removing the portion inside the opening 13A of the MOS I 2 film I2 used as a mask, an ion implantation method is applied to implant boron (B) ions to form a p-type well using IX 1013 ( The implantation is performed at a dose of approximately cm2).

Refer to FIG. 5. When a heat treatment called running is performed, a p-type well 2 as shown in the figure is formed.

See Figure 6 ■ 5i3Nsl by applying reactive ion etching method
Using the odor 11 as a mask, the silicon semiconductor substrate 1 is etched to form a fine groove 2A around the p-type well 2. In addition, when performing this etching, M o S i
2 film 12 may be removed.

1. See FIG. 7. By applying a thermal oxidation method or a CVD method to bury 5i02 or the like in the trench 2A, an insulating film 14 is formed around the p-type well 2 in a self-aligned manner.

[Phase] When the Si3N4 film 11 is removed, the state shown in the figure is obtained.

Refer to FIG. 8■ After this, by applying a normal technique, the gate electrode 3 of the n-channel transistor, the leakage + type impurity diffusion regions 4 and 5 for forming the n-channel transistor, the p + type ground contact region 6, Gate voltage of p-channel transistor @7, p+ for forming p-channel transistor
type impurity diffusion regions 8 and 9, an n+ type power contact region 10, an insulating film 15 made of, for example, 5LO2, and a source electrode 16 made of, for example, aluminum (Aβ). Drain electrode 17. Gate electrode 18. P-type well contact electrode 19. Source electrode 20. Drain electrode 21, gate electrode 22. The substrate contact electrode 23 and the like may be formed to have an 0MO3 structure. In addition, QN is an n-channel side transistor,
QP indicates a p-channel side transistor.

In the CMO3 semiconductor device manufactured in this way, an insulating film 14 was formed on the base of transistor Q2, which is a pnp transistor, among the parasitic bipolar transistors Q1 and Q2 explained with reference to FIGS. 1 and 2. It is clear that the current amplification factor of the transistor Q2 decreases and the resistor R2 becomes thicker.

Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, the surface of the semiconductor substrate is covered with a film that can be etched by reactive ions, and further covered with a photoresist to form a well of a conductivity type opposite to that of the semiconductor substrate. forming an opening in the photoresist at the desired location, removing the film at the periphery of the opening by reactive ion etching, and introducing an opposite conductivity type impurity into a region of the semiconductor substrate defined by the opening; forming a well, forming a groove in the semiconductor substrate at the same position as the removed portion of the film, and burying an insulator in the groove, thereby terminating the pn junction in the well with the insulator. Therefore, the insulator isolation around the well is self-contained.
It can be formed by alignment, and its width is 1 [μ
m] and is extremely fine, making it suitable for integrated circuits that require high density, and the resulting CM
In O3 semiconductor devices, the current amplification factor of the pnp (pnp) transistor, which is a parasitic bipolar transistor formed in the lateral direction, is significantly reduced, and a portion of the internal resistance becomes large, so that the latch amplifier As a result, the latch-up withstand voltage is improved.

[Brief explanation of drawings]

Fig. 1 is a cutaway side view of the main part of the conventional example, Fig. 2 is an equivalent circuit diagram of the main part to explain the relationship in which the parasitic bipolar transistor is generated in the conventional example of Fig. 11, and Figs. FIG. 8 is a cross-sectional side view of a CMO8 semiconductor device at important points in the process for explaining the manufacturing of an embodiment of the present invention. In the figure, ■ is an n-type semiconductor substrate, 2 is a p-type well, and 3 is a p-type well.
is the gate electrode of the n-channel transistor, 4 and 5 are n+ type impurity diffusion regions for forming the n-channel transistor, 6 is the p+ type ground contact region, 7 is the gate electrode of the p-channel transistor, and 8 and 9 are the gate electrodes of the p-channel transistor. p+ type impurity diffusion region for forming p-channel transistor, 1° is n+ type power supply contact region, 11 is silicon nitride (Si3N4) film, 12 is molybdenum silicide (
MoS+2) film, 12A is a groove, 13 is a photoresist film, 13A is an opening, 14 is an insulating film, 15 is an insulating film, 1
6 and 20 are source electrodes, 17 and 21 are drain electrodes, 18 and 22 are gate electrodes, 19 is a well contact electrode, 23 is a substrate contact electrode, QN is an n-channel side transistor, QP is a p-channel side transistor, vnt+ is the positive power supply level, Ql is a parasitic npn) transistor, Q2 is a parasitic pnp transistor, R1, R2, R3, R4, R
5 is an internal resistance. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - 3

Claims (1)

[Claims] covering a surface of the semiconductor substrate with a reactive ion etching film, further covering with a photoresist, and forming an opening in the photoresist in a portion where a well of a conductivity type opposite to that of the semiconductor substrate is to be formed; The film at the periphery of the opening is removed by reactive ion etching, an opposite conductivity type impurity is introduced into the semiconductor substrate area defined by the opening to form a well, and a well is formed at the same position as the removed portion of the film. 1. A method of manufacturing a semiconductor device, comprising forming a groove in a semiconductor substrate portion, burying an insulator in the groove, and terminating a pn junction in the well with the insulator.