JP2001291678A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, in which punch through breakdown voltage can be increased, without making the well deep. SOLUTION: The method for manufacturing a semiconductor device comprises a step for implanting N-type impurity ions into a P-type silicon substrate 1 with high acceleration energy in the order of MeV, a step for forming an N-type well by heat treating the silicon substrate 1 at a temperature of 1,100-1,200 deg.C, a step for making deeper the peak position in the impurity concentration of an N-type well 9 by performing counter dope of P-type impurities in the N-type well 9, a step for implanting P-type impurity ions into the N-type well 9, and a step for forming a P-type well 17 in the N-type well 9 by heat treating the silicon substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a well. In particular, the present invention relates to a method for manufacturing a semiconductor device capable of increasing punch-through breakdown voltage without increasing the depth of a well.

[0002]

2. Description of the Related Art FIGS. 8A to 8C are cross-sectional views showing a conventional method for manufacturing a semiconductor device. FIG. 8D shows FIG.
13 is a graph showing a relationship between the substrate depth indicated by an arrow C1 and the impurity concentration in the semiconductor device shown in FIG.

This method of manufacturing a semiconductor device includes a step of forming a triple well.
It is performed by heat diffusion (drive-in) for a long time at an extremely high temperature of 0 ° C. or more. Hereinafter, a specific description will be given.

First, as shown in FIG. 8A, a silicon oxide film 103 is formed on a surface of a P-type silicon substrate 101 by a thermal oxidation method. Next, a silicon nitride film is deposited on the silicon oxide film 103, and a resist film (not shown) is applied on the silicon nitride film. Next, a resist pattern is formed on the silicon nitride film by exposing and developing the resist film. Thereafter, by etching the silicon nitride film using the resist pattern as a mask, a nitride film pattern 105 located on the P-well formation region is formed on silicon oxide film 103. Next, an N-type impurity 107 is ion-implanted into the P-type silicon substrate 101 using the nitride film pattern 105 as a mask.
Thereby, the N-well region 1 of the P-type silicon substrate 101
09 is doped with N-type impurity ions. As the ion implantation conditions at this time, for example, P is used as the N-type impurity 107, and a low acceleration energy of about 120 KeV is used.

Next, as shown in FIG. 8B, the P-type silicon substrate 101 is thermally oxidized using the nitride film pattern 105 as a mask, thereby forming a film on the N-well region 109 of the P-type silicon substrate 101. Thick oxide film 103a is formed. Thereafter, the nitride film pattern 105 is peeled off, and the P-type silicon substrate 101 is formed using the thick oxide film 103a as a mask.
, A P-type impurity 111 is ion-implanted. This allows P
P-type impurity ions are introduced into P-well region 113 of type silicon substrate 101.

Next, as shown in FIG. 8C, the P-type silicon substrate 101 is subjected to a heat treatment (drive-in) at a temperature of, for example, 1210 ° C. for about 16 hours, so that the N-well 109 and the P-well 113 are respectively formed. Is thermally diffused. Thereafter, after the thick oxide film 103a and the silicon oxide film 103 are peeled off, a silicon oxide film 115 is formed on the entire surface of the P-type silicon substrate 101 by a thermal oxidation method.

Next, a resist pattern is formed on the silicon oxide film 115 by applying a resist film on the silicon oxide film 115 and exposing and developing the resist film. Thereafter, the N-well 10 of the P-type silicon substrate 101 is formed using the resist pattern as a mask.
P-type impurities (not shown) are ion-implanted into the triple well region 117 in FIG.

Next, for example, 1
Heat treatment at 210 ° C for about 8 hours (drive-in)
, The triple well 117, N well 1
09 and P well 113 are thermally diffused.

[0009]

In the above-described conventional method for manufacturing a semiconductor device, impurity ions are introduced into the vicinity of the surface of the silicon substrate 101 and subjected to a heat treatment at an ultra-high temperature of 1200 ° C. or more for a long time. As a result, a deep N well 109 is formed in the silicon substrate 101. In this method, since the impurity concentration becomes lower as the well becomes deeper, as shown in FIG. 8D, the N well 109 below the triple well 117 has a lower concentration. Therefore, in order to ensure the punch-through withstand voltage between the silicon substrate 101 and the triple well 117, the heat treatment time for forming the well must be increased to increase the length of the N well 109 in the depth direction. However, when such a long-time heat treatment is performed, the impurities diffuse not only in the depth direction but also in the lateral direction, so that the wells spread in the lateral direction, the rules of the wells are loosened, and the integration density of the semiconductor element is reduced. Is a factor of decrease.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device which can increase punch-through breakdown voltage without increasing the depth of a well. It is in.

[0011]

According to a method of manufacturing a semiconductor device according to the present invention, a first conductivity type impurity is added to a semiconductor substrate in an amount of 2.0%.
A first step of implanting ions at an acceleration energy of MeV or more and 5.0 MeV or less, and a second step of forming a first conductivity type well by performing a heat treatment on the semiconductor substrate at a temperature of less than 1200 ° C. for 8 hours or less. A third step of ion-implanting a second conductivity type impurity into the first conductivity type well, and a second step in the first conductivity type well by heat treating the semiconductor substrate.
And a fourth step of forming a conductive well.

According to the method of manufacturing a semiconductor device, the first
In the process, the first conductivity type well is formed by ion-implanting the first conductivity type impurity into the semiconductor substrate at a high acceleration energy of MeV order. Therefore, the first conductivity type well has an impurity concentration peak inside, and the impurity concentration of the first conductivity type well can be increased. Therefore, the punch-through withstand voltage can be increased without increasing the depth of the well.

Further, in the method of manufacturing a semiconductor device according to the present invention, the second conductive type impurity is ion-implanted into the first conductive type well between the second and third steps. The peak position of the impurity concentration in the
It is preferable to add a step of making the well deeper than the well of the first conductivity type after the step. In this way, the second well of the first conductivity type is
By counter-doping the conductivity type impurities, the impurity concentration of the first conductivity type well in the vicinity of the junction between the first conductivity type well and the second conductivity type well can be reduced. Therefore, a high junction breakdown voltage can be secured between the first conductivity type well and the second conductivity type well.

In the method of manufacturing a semiconductor device according to the present invention, a first conductivity type impurity is added to a semiconductor substrate at a concentration of 2.0 MeV or more and 5.0 or more.
A first step of implanting ions at an acceleration energy of MeV or less, a second step of forming a first conductivity type well by performing a heat treatment on the semiconductor substrate at a temperature of less than 1200 ° C. for 8 hours or less, and a first conductivity type well Ion implantation of a second conductivity type impurity into the well to make the impurity concentration peak position of the first conductivity type well deeper than the first conductivity type well immediately after the second step. It is characterized by.

According to the method of manufacturing a semiconductor device, the third
Since the first conductivity type well is counter-doped with the second conductivity type impurity in the process, the peak position of the impurity concentration of the first conductivity type well can be further deepened. As a result, the impurity concentration of the first conductivity type well in the vicinity of the junction between the first conductivity type well and the second conductivity type well can be reduced. Therefore, a high junction breakdown voltage can be secured between the second conductivity type well and the first conductivity type well.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the first conductivity type impurity ion-implanted in the first step has a concentration peak located at a depth of 3 μm or more from the surface of the semiconductor substrate. .

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 7 are views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method of manufacturing a semiconductor device includes a step of forming a medium-voltage triple well without using ultra-high temperature thermal diffusion (drive-in). Hereinafter, a specific description will be given.

First, as shown in FIG. 1, a silicon oxide film 3 is formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method. Next, a CVD (Chemical) is formed on the silicon oxide film 3.
A silicon nitride film is deposited by a vapor deposition method, and a resist film (not shown) is applied on the silicon nitride film. Thereafter, the resist film is exposed and developed to form a resist pattern on the silicon nitride film. Next, by etching the silicon nitride film using the resist pattern as a mask, a nitride film pattern 5 located on the P well formation region is formed on the silicon oxide film 3. Thereafter, N-type impurity 7 is ion-implanted into P-type silicon substrate 1 using nitride film pattern 5 as a mask. Thereby, N-type impurity ions are introduced into N-well region 9 of P-type silicon substrate 1. The ion implantation conditions at this time are, for example, using P as the N-type impurity 7,
The acceleration energy is 2.0 to 5.0 MeV (preferably 4.4 MeV), and the dose is 1.0 × 10 ^{13 to} 3.0 ×.
It is 10 ¹³ cm ^-2 (preferably 2.50 × 10 ¹³ cm ^-2 ).

Next, as shown in FIG. 2, the P-type silicon substrate 1 is subjected to wet oxidation at a temperature of about 1010 ° C. for about 1.5 hours using the nitride film pattern 5 as a mask. A thick oxide film 3a is formed on N well region 9 of FIG.

Thereafter, as shown in FIG. 3, the nitride film pattern 5 is peeled off, and P-type impurities 11 are ion-implanted into the P-type silicon substrate 1 using the thick oxide film 3a as a mask. Thereby, P-type impurity ions are introduced into P-well region 13 of P-type silicon substrate 1. The ion implantation conditions at this time are as follows:
For example, B is used as the P-type impurity 13, the acceleration energy is 40 to 60 KeV, and the dose is 1.0 × 10 ¹³ to
2.0 × 10 ¹³ cm ⁻² (preferably 1.50 × 10 ¹³ c
m ^-2 ).

Next, as shown in FIG. 4A, heat treatment (drive-in) is performed on the P-type silicon substrate 1 at a high temperature of, for example, less than 1200 ° C. (preferably 1100 ° C. to 1200 ° C.) for about 2.5 hours. By applying N well 9 and P
The impurities in each of the wells 13 are thermally diffused. Thereby, an N well 9 having an impurity concentration distribution as shown in FIG. 4B is formed on the P-type silicon substrate 1. That is, since the N-type impurity 7 is ion-implanted (mega-implanted) with high acceleration energy in the step shown in FIG.
The peak P1 of the impurity concentration of the N well 9 can be formed at a substrate depth of 3 to 4 μm. FIG.
The relationship between the impurity concentration and the substrate depth of the silicon substrate 1 located at the arrow C2 shown in FIG.

After the thick oxide film 3a and the silicon oxide film 3 are peeled off, a silicon oxide film 15 is formed on the entire surface of the P-type silicon substrate 1 by a thermal oxidation method.

Next, as shown in FIG. 5A, the entire surface of the P-type silicon substrate 1 is counter-doped with P-type impurity ions 16 having a conductivity type opposite to that of the N well 9. The ion implantation conditions at this time are, for example, B ions as the P-type impurity ions 16, an acceleration energy of 1.0 to 2.0 MeV,
The dose is set to 8.0 × 10 ^{12 to} 1.0 × 10 ¹³ cm ⁻² (preferably 9.0 × 10 ¹² cm ⁻² ). This allows
An N well 9 having an impurity concentration distribution as shown in FIG. 5B is formed on the P-type silicon substrate 1. That is, the peak P of the impurity concentration of the N well 9 due to the counter doping.
2 is formed at a substrate depth of 5 to 6 μm. FIG. 5 (b)
6 shows a relationship between the substrate depth of the silicon substrate 1 located at the arrow C3 shown in FIG. 5A and the impurity concentration.

Thereafter, as shown in FIG. 6, a resist pattern is formed on the silicon oxide film 15 by coating a resist film on the silicon oxide film 15 and exposing and developing the resist film. . Thereafter, a P-type impurity 19 is ion-implanted into the triple well region 17 in the N-well 9 of the P-type silicon substrate 1 using the resist pattern 18 as a mask. The ion implantation conditions at this time include, for example, B as the P-type impurity 19 and an acceleration energy of 1.2.
The dose is about MeV and the dose is about 1.80 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 7A, the P-type silicon substrate 1 is heated at a temperature of, for example, 1100 ° C. to 1200 ° C.
By performing heat treatment (drive-in) for about an hour,
The impurities in the triple well 17 are thermally diffused to form a triple well 17 having a medium withstand voltage (for example, about 20 V) on the silicon substrate 1. Thereby, the triple well 17 and the N well 9 having the impurity concentration distribution as shown in FIG. 7B are formed on the P-type silicon substrate 1. FIG. 7 (b)
Shows the relationship between the impurity concentration and the substrate depth of the silicon substrate 1 located at the arrow C4 shown in FIG.

According to the above-described embodiment, the N well 9 is formed by ion-implanting impurities into the P-type silicon substrate 1 with MeV-order acceleration energy in the step shown in FIG. Therefore, the N well 9 is shown in FIG.
Has an impurity concentration peak P3 inside, as a result, the impurity concentration of the N well 9 can be increased. Therefore, the punch-through withstand voltage can be increased without increasing the depth of the well. In other words, since it is not necessary to form the N-well deeply as in the conventional method of manufacturing a semiconductor device, it is not necessary to perform thermal diffusion at a high temperature of 1200 ° C. or more. In addition, a reduction in the degree of integration of the semiconductor element can be suppressed.

In other words, as shown in FIG. 7B, the retrograde distribution has an internal peak such that the impurity concentration peak of the triple well 17, the N well 9 and the P-type silicon substrate 1 is placed in the N well 9. By doing
The punch-through withstand voltage can be ensured without increasing the length of the N well 9 in the depth direction.

Further, by increasing the impurity concentration of the N-well 9 to have a retrograde distribution as described above, the amplification factor of the parasitic bipolar transistor can be suppressed low, and the resistance to latch-up can be increased.

In the above-described embodiment, since the P-type silicon substrate 1 is counter-doped with B in the step shown in FIG. 5, the triple well 1 is formed as shown in FIG.
The impurity concentration of the N well 9 in the vicinity of the junction between the N well 9 and the N well 9 can be reduced. Thereby, a high junction breakdown voltage between the triple well 17 and the N well 9 can be secured.

The present invention is not limited to the above-described embodiment, but can be implemented with various modifications. For example,
In the semiconductor device according to the above-described embodiment, it is also possible to use a semiconductor device having the opposite conductivity type.

[0031]

As described above, according to the present invention, the first conductivity type well is formed by ion-implanting the first conductivity type impurity into the semiconductor substrate at a high acceleration energy of the order of MeV. Therefore, it is possible to provide a method of manufacturing a semiconductor device capable of increasing punch-through breakdown voltage without increasing the depth of the well.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a cross-sectional view showing a step subsequent to FIG.

FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a cross-sectional view showing a step subsequent to FIG.

FIG. 4A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to FIG. 3, and FIG. 9 is a graph showing a relationship between a substrate depth indicated by an arrow C2 and an impurity concentration in a semiconductor device.

FIG. 5A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to FIG. 4A, and FIG. 13 is a graph showing a relationship between a substrate depth indicated by an arrow C3 and an impurity concentration in the semiconductor device shown in FIG.

FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a cross-sectional view showing a step subsequent to FIG.

FIG. 7A is a cross-sectional view showing a method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to FIG. 6, and FIG. 7B is a sectional view showing FIG. 13 is a graph showing a relationship between a substrate depth indicated by an arrow C4 and an impurity concentration in a semiconductor device.

FIGS. 8A to 8C are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device. FIG. 8D is a graph showing the relationship between the substrate depth and the impurity concentration indicated by an arrow C1 in the semiconductor device shown in FIG. It is a graph which shows a relationship.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 3 Silicon oxide film 3 a Thick oxide film 5 Nitride film pattern 7 N-type impurity 9 N-well 11 P-type impurity 13 P-well 15 Silicon oxide film 16 P-type impurity 17 Triple well 18 Resist pattern 19 P-type impurity 101 P-type silicon substrate 103 Silicon oxide film 103a Thick oxide film 105 Nitride film pattern 107 N-type impurity 109 N-well 111 P-type impurity 113 P-well 115 Silicon oxide film 117 Triple well P1-P3 Peak impurity concentration C1-C4 Arrows

Claims (4)

[Claims] A first conductivity type impurity added to the semiconductor substrate;
A first step of ion-implanting with an acceleration energy of MeV or more and 5.0 MeV or less, and a second step of forming a first conductivity type well by performing a heat treatment on the semiconductor substrate at a temperature of less than 1200 ° C. for 8 hours or less. A third step of ion-implanting a second conductivity type impurity into the first conductivity type well; and a fourth step of forming a second conductivity type well in the first conductivity type well by heat treating the semiconductor substrate. A method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the second conductive type impurity is ion-implanted into the first conductive type well between the second and third steps, thereby setting the impurity concentration peak position of the first conductive type well to the second conductive type well.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of making the well deeper than the well of the first conductivity type after the step. 3. The method according to claim 1, wherein the first conductivity type impurity is added to the semiconductor substrate in an amount of 2.0%.
A first step of implanting ions with an acceleration energy of MeV or more and 5.0 MeV or less, a second step of forming a first conductivity type well by performing a heat treatment on the semiconductor substrate at a temperature of less than 1200 ° C. for 8 hours or less; A third step of ion-implanting a second conductivity type impurity into the one conductivity type well to make the impurity concentration peak position of the first conductivity type well deeper than the first conductivity type well immediately after the second step; A method for manufacturing a semiconductor device, comprising: 4. The first conductivity type impurity ion-implanted in the first step has a concentration peak located at a depth of 3 μm or more from the surface of the semiconductor substrate. 2. The method for manufacturing a semiconductor device according to claim 1.