JPS6074453A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enlarge the process controlling margin of the title semiconductor device by a method wherein an SiO2 film is buried by performing a reactive ion etching (RIE) method having etching speeds different between a resist film located on the protruded part of the SiO2 film and an SiO2 film. CONSTITUTION:A thermally oxidized film 22 is formed on a P type Si substrate 21, and a recessed part 23 is formed by performing an RIE method. Then, a P<+> layer 24 which will be turned to a channel stopper, an SiO2 film 25 and a resist film 26 are formed. Subsequently, a resist film 27 is formed on the whole surface. Then, an etching is performed using an RIE method. At this time, the etching speed of the film 25 is to be set higher than that of the film 27. Then, resist films 26 and 27 are removed.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device. This relates to a method for manufacturing a semiconductor device (F) in which a semiconductor device (F) is embedded flatly. [Technical background of the invention and its problems] A semiconductor device using silicon as a semiconductor, especially MO8
In one row of type semiconductor devices, a thick oxide film is formed in a so-called field region between elements in order to eliminate insulation defects due to parasitic channels and to reduce the amount of parasitic customers. A selective oxidation method is well known as a method for isolating elements using such an oxide film. This involves covering the element forming area with an oxidation-resistant mask, typically using a silicon nitride film, and performing high-temperature oxidation to selectively thicken the field area by +1! a
It forms the However, in such a selective oxidation method, the edge of the oxide film digs into the silicon during high-temperature oxidation in a bird's beak pattern, causing dimensional errors in the device formation area, and The reduction in element size has been an obstacle to increasing the S density of integrated circuits. In addition, in the selective oxidation method, after forming a field hardening film, a surface step difference of about half the field oxidation thickness is formed between the field region and the element formation region. This remains as a step until later steps, resulting in lower reliability such as lower lithography accuracy and disconnection of metal wiring at the step. On the other hand, in order to eliminate the bird's beak and to flatten the surface, there is a device diode II method in which one field region of the semiconductor substrate is etched and, in particular, an insulating film is buried. This element is 1! An example of the +fa method will be explained using FIG. 6111. First, as shown in FIG. 1 (FL), an etching-resistant mask 12 is formed in the element formation region of the Si substrate 11 7, and the substrate 1 is
1 and etched the 111st tl (1
3 is formed in the field area. koo)r, t□, ion implantation using the same mask 12, field inversion 5)
Ion j1゛layer 14'' for j stop: j7 type 1.+i
;、-Jru. For example, if the group 1 and 11 are p-type, -geron is implanted. The Buddha, the tail as shown in (b), this 71
−; CVD on the entire board surface to J-segment, which is equivalent to the step of recess J3.
- Deposit S+02 film 15. Then, as shown in (c), the surface is flattened using Renost II) J 76 Rusbin Coat 1 to 5 for flattening. After this, resist piece 7
．． Reactive ion etching (ROC) method with conditions set so that the etching rate was 'Y11 for CVD-5i0211j15 (the entire surface was etched from the hair, (d) CVD-51 as shown in Ic)
Obtain a state in which 02Qf-, 15 is flatly embedded in the -y4-/l/t region. Thereafter, desired elements are formed in nine element forming regions. However, in this conventional method, CVD-5i02 film 1
In order to sufficiently flatten the surface unevenness after depositing the 5i02 bulge 15, the resist film 16 needs to have a thickness of 3 μm or more on the convex portion of the 5i02 swelling 15. Such a thick resist film 1
It is difficult to uniformly etch 6 by RIE. For example, when trying to suppress the variation in the thickness of the 5i02 flk to be embedded to about 5 lines or less (A:, the variation due to etching of the resist film must also be suppressed to about the same level or less, but the etching speed of normal RIE is only limited to this. It is difficult to achieve accuracy. By setting the RIE conditions,
If the etching rate is slowed to, for example, 400 Vrnin Q degrees, a 3 μm resist film and a 0.6 μm 5iO
It takes about 90 minutes to etch the Z film. This not only causes jG (JG) of the cost sieve, but also causes variations in film thickness due to longer processing time. [Objective of the Invention] The present invention provides f? A semiconductor device 11j in which a field insulating film with no variation in 'INJ'1 is embedded in a recess formed in a field region of a semiconductor substrate in a final process to improve device reliability and yield.
The purpose is to provide a manufacturing method for. [Invention of Il! [required for l]] The method of the present invention first begins with a semi-J″y body; j, +: A+i
A surface 1 etching mask is formed on the field i and field II.
Selectively etching 2 to form a concave part, then remove the 1liJ etching mask to form a concave part 1"'
G4. ) with early 1 filtration 4 lower, 11.;'1 deposited. Then, when turning to the field 7 (L (area)) of this insulating film, a ribbon with a thickness equivalent to the step of the concave portion is selectively formed using the normal copy J' (, % jl (,!; After this, Yodo 5 amphoteric material (+j' 11・,!) is formed on the entire surface (
j': Form the cloth to smooth out the unevenness of the surface caused by the above-mentioned termination (S, 1, 2!). At this time, the cloth is formed.
．． + II: itiwa'i1.11・Winter is groove-, It
, so that the surface position ii, +( is lower than the surface f ~ Z111 of the convex portion of IFx),

[:I
It's a big formation. Then, the etching speed for the insulating film is lower than that for the self-flowing material A. Etching is performed on the entire surface using the etching method. Selectively embed the insulating film. At this time, the etching rate for the waver film may be equal to or lower than that for the insulating film. In this way, a desired element is formed in the element formation region separated by the flat buried insulating film. [Effects of the Invention] According to the present invention, it is not necessary to perform a complete surface planarization process before etching the insulating film, and it is not necessary to equalize the etching speed for films of different materials, making it easy to set etching conditions. This expands the range of material selection and increases the margin of process control. Furthermore, since the fluid material film is made thin, a buried insulating film with very little variation can be obtained without requiring a long time for etching. Therefore, according to the present invention, it is possible to improve the yield and reliability of semiconductor devices. [Embodiments of the Invention] Examples of the present invention will be described below with reference to FIG. 2. First, P with plane orientation (100) and specific resistance of 5 to 10 Ω-rm
A type Si substrate 21 is prepared, and a thermal oxidation band 22 of, for example, 4000λ is formed thereon to serve as a one-control etching mask and a control ion implantation mask. The field area 1c was created using the 3D etching method, and the depth was 0.6tx with an angle of 546°.
rn fli! To form a recess 23 at 6 1u, the B+ ions were heated at 50 KV at I x 10" Am2
P layer 24 which becomes a channel stopper by implanting ions to a certain extent
(a). Next, remove the thermal oxidation rib 22 and
, C, thermal oxidation of about 500
25? IT about 0.611m or thicker
'Ct (b). Next, on the concave portion of the surface of this S + 02 1 barrier 25, place the 4--ri 11-2 "(,?) 11
1 Photo L'Cfi of Lillenost membrane 26! II engraving method j
' Form selectively (c). At this time, the distance 1ijlfi x from the periphery of the recess 23 to the resist film 26 is 11
1st, stage 7 of lX23' 0.2T when A4T
1-rotate so that ≦X≦5T. Further, the film J7 of the resist film 26 is made, for example, about 0.6 μm, as is the step difference in the recessed portion 23. After that, a positive resist is used as a fluid material film! 5i-27 is applied to the entire surface to smooth the boundary between the resist film 26 and the Sioz I pattern 2s (d). At this time, ? The di-type resist film 27 is
The convex part of the uneven surface formed by the 5102 film 25 and the resist film 26 is about 0.2 μm, and the concave part, that is, the groove part, is about 0.611 m.
It is formed thinly so that it is below and lower than the surface position of the convex portion of the 5i02 film 25. Next, the entire surface is etched by a reactive ion etching method using Freon gas. At this time, the etching conditions were 5102 N'
The etching rate of the resist group 25 is set to be higher, for example, about twice that of the resist group 27, and the entire surface is etched until the surface of the substrate in the element formation region is exposed. Figure 3 shows the measured data of the error rate of CVD-5102 and resist when the flow rate of CF4 was kept constant at 24 ml/ml, the RF power was 150 W, the pressure was 10 mTorr, and the H2 flow rate was changed. . These, 5io2
The etching speed +-W of the film 25 is twice that of the resist 11 (27), and the etching conditions are ■■2 streams (,; is approximately 4 mVmi
ai at point n). In this native, etching series 1r1.
- is relatively large and stable, and the etching margin is thick (・.Also Renost 1]・Co, 27 no 3 + 021
1ψ25 and the difference between the thickness of the convex part and the thickness of the groove part by the resist film 26, I-(2) By changing the ridge 1, a part of the resist film 26 and 27 is fielded as shown in (e). It is easy to set the etching conditions of 11" to expose the element expansion area while leaving the retention area on the area. After this, the 02 asher is applied to the 11" etching condition. 26 and 27 are removed (f). Then, the temperature is increased to 2° C. to form, for example, a polysilicon layer MOSFET. As mentioned above, the resist film 26 is RITi; This Renost film 2 is used as a H retaining film to prevent the 5i02 film 25 in the field region from being etched in the process (from Q<,
It is preferable that the etching speed of the SiO2 film 2.6 is also lower than that of the SiO2 film 2.6. However, is there an eye on this regimen film 26? Since the di-type resist 27 is thinly attached, its etching rate may be about the same as that of the 5i02 film. As described above, in this example, without completely flattening the substrate surface before etching the 5io2 film, the resist film on the convex portion of the s102 film is made very thin, and the resist film, sio, and film are etched together. The 5i02 film is embedded by an RIE process with different speed conditions. Therefore, it is easy to set etching conditions, there is a large margin for process control, and the etching time is short.
, it is possible to obtain a field insulating layer with less variation in thickness. Furthermore, since the etching time is short, costs can be reduced. In addition, the mask alignment margin when forming the subaree l/distor] 26 is sufficient as it is between 0.2T and 5T for the film T of 5i02111.25, and is sufficiently large, taking alignment deviation into account. Since it is not necessary, the device can be highly integrated. Furthermore, the resist film 27 is not intended to be completely flattened, but may be applied thinly as a whole so as to have a certain masking effect in the grooves, so the resist film 27 is not completely flattened.
There is a wide range of kits to choose from. The present invention is not limited to the second embodiment. For example, in the above embodiment, the case where the 5i02 film layer was used as a mask for etching the Si substrate was explained, but the S+02/
As a two-layer structure of poly-Si, Si substrate etching & i
S 10211E k Mask Toshi”'C conduct, Hori 5
i11! ', 'J may be used as a 'C stopper' during RIE of CVD-S+02 film embedding after sonography. I'm scared, S I nol! , IJQ'4" (R side
IB can prevent you from receiving state injuries. Others are Po1y-St covered with SiO□. SiN single layer or S 102 /S iN % A, lJ
203/']? IJ such as St, A6203/SIN, etc.
I can't even think of a 4th intersection. In addition to the Lenost N statue, the Moon? It is also possible to use a metal film such as S i-, inorganic resist, or AI, or a fluid material film such as spin-on glass 1.1? It is also possible to use JT and limide, PSG, etc. Also, M1 in the field area! Ill<! In addition to CVD-SiO□, snow and ivy methods, and plasma
5i02, SiN, Po1y by CVD method
-81. An insulating film such as an Al2O3 film may be used, and a composite film thereof may also be used.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are construction diagrams illustrating an example of the conventional element 1'al method, and FIGS. 2(a) to (f) are process diagrams illustrating one embodiment of the present invention. FIG. 3 is a diagram showing experimental data regarding etching rate determination by RIE. 2...Si base plate, 22...Thermal oxidation +124S, 23
... recess (field area), 24 ... P ten layers, 2
5...CVD-5i0211! ↓, 26... Renost film (spacer film), 27..., J? Di-type resist film (fluid material film).

Claims (3)

[Claims] (1) A step of forming a recess in the field region of a semiconductor substrate, a step of depositing an insulating film with a thickness equal to or greater than the Shitoman-W difference over the entire surface of the substrate in which the recess is formed, and A step of selectively forming a spacer film having a thickness equivalent to the step of the recess on the field region, and applying a fluid material film to the entire surface of the substrate on which the spacer film is formed so that the surface position at the groove is insulating. The insulating film is selectively etched in the field region by etching the entire surface using a step of forming the insulating film thinly at a level lower than the surface position of the convex portion and an etching method in which the etching rate for the insulating film is higher than that for the fluid material film. A method of manufacturing a semiconductor device, comprising the steps of embedding and forming a desired element in the element formation region. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the spacer film is a resist film, and the fluid material film is a resist film of the same type or a different glaze. (3) The semiconductor according to claim 1, wherein the spacer film is formed at a distance of 0.2T to 5T from the periphery of the recess, where T is the film JI, f' of the insulating film. Method of manufacturing the device.