JPH049380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an element isolation region, and particularly to a method for forming an element isolation region that can be miniaturized in a silicon integrated circuit.

[Conventional technology]

Selective oxidation method (LOCOS method) has been widely used as an element isolation method for silicon integrated circuits.
is 1μm due to lateral penetration of the oxide film.
Not suitable for element isolation smaller than width. Therefore, as a method that can isolate minute elements, we use the "trench isolation method," which involves digging trenches in a silicon substrate and filling the trenches with an insulating film.
is being considered. However, although the conventional groove separation method is suitable for separating narrow groove widths, it has the disadvantage that it is not possible to fill groove widths at two or more points in the film thickness.

For this reason, a method has been proposed in which an insulating film is left in a wide trench. One method is to use lift-off,
The other method is etching using a mask.

[Problem that the invention seeks to solve]

The above-mentioned lift-off method can embed an insulating film regardless of the groove width with one alignment exposure.
However, the manufacturing method is difficult and it is difficult to manufacture with good yield. On the other hand, the method of etching using a mask is easy to manufacture, except that the number of alignment exposures increases by one. However, unless measures are taken to prevent misalignment, there is a drawback that the finished shape will lack reproducibility.

An object of the present invention is to provide a method for forming an element isolation region that embeds an insulating film with good reproducibility regardless of the groove width with only one alignment exposure for forming the groove, and does not generate crystal defects. shall be.

[Means for solving problems]

The method for forming an element isolation region of the present invention includes the steps of forming a groove on one main surface of a single crystal silicon substrate, and forming a thermal oxide film, a silicon nitride film, and the silicon nitride film on one main surface of the substrate in which the groove is formed. A step of sequentially forming a polycrystalline silicon film with a thickness of approximately 1/2 of the trench depth, a step of spin-coating an organic polymer resin film on the polycrystalline silicon film, and a step of coating the polycrystalline silicon film with the polycrystalline silicon film. a step of uniformly etching only the surface portion of the organic polymer resin film so that the organic polymer resin film remains only inside the groove; and a step of etching the organic polymer resin film left inside the groove as a mask; The method includes a step of etching the polycrystalline silicon film so that it remains substantially flat in the trench, and a step of thermally oxidizing the polycrystalline silicon film remaining in the trench.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1a to 1f are cross-sectional views shown in order of steps to explain an embodiment of the present invention. This example can be implemented through the following steps.

First, as shown in FIG. 1A, grooves 3 are formed in a single crystal silicon substrate 1 using, for example, a photoresist film 2 as a mask using anisotropic etching such as reactive sputter etching. In etching, if a photoresist film cannot be used as a mask due to poor selectivity with silicon, an oxide film is used as a mask. The depth of the groove to be formed may be about 0.5 μm to 1 μm when separating MOS transistors. If the silicon substrate concentration is low, in order to prevent the formation of an inversion layer at the bottom of the trench, after etching the silicon, ions are implanted using the photoresist film 2 as a mask to form a channel stopper.

Next, as shown in FIG. 1B, a thermal oxide film 4 of about 500 Å is formed, and then a nitride film 5 of about 1000 to 2000 Å is formed by vapor phase growth. Next, a polycrystalline silicon film 6 having a thickness of about 1/2 of the depth of the groove is formed.
Subsequently, an organic polymer resin film 7 is spin-coated.
As the organic polymer resin film, photoresist film,
A polyimide film, an organic silicon resin film, or the like can be used.

Next, as shown in FIG. 1c, the surface is uniformly coated so that the organic polymer resin film 7a remains only inside the groove.
Etch using O ₂ plasma or the like.

Next, as shown in FIG. 1d, the polycrystalline silicon film 6 is etched using anisotropic etching such as reactive sputter etching using the organic polymer resin film 7a as a mask. At this time, the time required for etching the polycrystalline silicon film is 2
If the etching time is doubled, polycrystalline 6a will be formed in the groove.
can be left flat. In this etching, it is necessary to have a selectivity ratio of at least 10 between polycrystalline silicon and the nitride film.

Next, the organic polymer resin film 7a is removed and the polycrystalline silicon film 6a is thermally oxidized. At this time, the silicon substrate 1 is not oxidized because it is covered with the nitride film 5. The polycrystalline silicon film within the trench expands approximately twice in the thickness direction due to thermal oxidation. Therefore, since no stress is applied to the silicon substrate due to thermal oxidation, no crystal defects are generated. Further, after oxidation, the substrate surface and the oxide film 8 almost coincide as shown in FIG. 1e.

Next, as shown in FIG. 1F, the nitride film 5 and thermal oxide film 4 are etched to expose the surface of the silicon substrate 1, thereby completing the element isolation region of this embodiment.

Note that when manufacturing a MOS transistor using this, it is sufficient to form a gate oxide film on the surface and then continue with the normal MOS process.

FIGS. 2a to 2c are cross-sectional views of the main steps shown in the order of steps to explain the second embodiment of the present invention. In FIGS. 2a to 2c, a case will be explained in which the groove width is relatively wide as described so far, and a case where the groove is the same or smaller than the groove depth.

First, as shown in FIG. 2A, since the trench 9 has a narrow groove width, when the polycrystalline silicon film 6 is formed, the trench 9 is completely filled with polycrystalline silicon.

Next, as shown in FIG. 2b, when the organic polymer resin film 7 is etched back, no organic polymer resin film remains in the grooves 9.

Next, as described in the first embodiment, the polycrystalline silicon film is etched under the conditions that twice the film thickness is etched, so that it can be etched regardless of the groove width, as shown in FIG. 2c. , polycrystalline silicon 6 in the groove
a and 6b can be left.

The subsequent steps are similar to those shown in FIG. 1 e and subsequent steps to complete the second embodiment.

As explained above, in the present invention, the organic polymer resin film has appropriate viscosity and curing properties, and when spin-coated onto a silicon substrate with grooves formed, a horizontal surface is required regardless of the unevenness of the underlying surface. This method takes advantage of the fact that it can be formed with hardness, that is, it adheres thickly to concave areas and thinly to convex areas, making the surface almost uniform, so if it is uniformly etched, the organic polymer resin film can be applied only to the concave areas. You can leave it behind. When this film is used as a mask for etching, a constant thickness of the polycrystalline silicon film can be left in the trench regardless of the trench width. Moreover, since the thickness of polycrystalline silicon is about 1/2 of the depth of the trench, the inside of the trench can be completely filled by thermal oxidation. Further, since the polycrystalline silicon film is separated from the silicon substrate by the nitride film, only the polycrystalline silicon film is thermally oxidized. Therefore, since the substrate is not affected by thermal oxidation, the occurrence of crystal defects can be suppressed.

〔Effect of the invention〕

As explained above, according to the present invention, the oxide film is left in the trench, so complete element isolation can be achieved. Furthermore, since only polycrystalline silicon is oxidized during oxidation, no crystal defects occur in the silicon substrate. It should be noted that the reproducibility is good and the insulating film can be easily filled in with just one alignment exposure to form the groove regardless of the width of the groove.

[Brief explanation of drawings]

1A to 1F and 2A to 2C are cross-sectional views shown in order of steps for explaining the first and second embodiments of the present invention, respectively. 1... Silicon substrate, 2... Photoresist film, 3... Groove, 4... Thermal oxide film, 5... Nitride film,
6, 6a, 6b...polycrystalline silicon film, 7, 7a
...Organic polymer resin film, 8...Oxide film, 9...Narrow groove.

Claims (1)

[Claims] 1. A step of forming a groove on one main surface of a single crystal silicon substrate, and forming a thermal oxide film, a silicon nitride film, and a silicon nitride film on one main surface of the substrate in which the groove is formed, and approximately 1/1/2 the depth of the trench.
2 steps of sequentially forming a polycrystalline silicon film with a thickness of A step of uniformly etching only the surface portion of the organic polymer film so that the polymer resin film remains; and a step of etching the polycrystalline silicon film inside the groove using the organic polymer resin film left inside the groove as a mask. 1. A method for forming an element isolation region, comprising the steps of: etching the polycrystalline silicon film so that the polycrystalline silicon film remains substantially flat; and thermally oxidizing the polycrystalline silicon film left in the trench.