JPS6074319U - FET amplifier - Google Patents

FET amplifier

Info

Publication number
JPS6074319U
JPS6074319U JP16545883U JP16545883U JPS6074319U JP S6074319 U JPS6074319 U JP S6074319U JP 16545883 U JP16545883 U JP 16545883U JP 16545883 U JP16545883 U JP 16545883U JP S6074319 U JPS6074319 U JP S6074319U
Authority
JP
Japan
Prior art keywords
fet amplifier
gate
amplifier
current detection
bias control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16545883U
Other languages
Japanese (ja)
Inventor
麻生 真成
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP16545883U priority Critical patent/JPS6074319U/en
Publication of JPS6074319U publication Critical patent/JPS6074319U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図はこの考案の構成図であり、図中1はRF回路部、2
は入力端子、3は前段増幅器、4は後段増幅器、5は出
力端子、6はゲートバイアス回路、7はGaAsFET
、8はドレインバイアス回路、9はゲート電流検出回路
、10は外部バイアス回路、11は電圧比較回路、12
はゲートバイアス制御回路、13はドレインバイアス制
御回路、14は電源である。
The figure is a configuration diagram of this invention, in which 1 is the RF circuit section, 2
is an input terminal, 3 is a front stage amplifier, 4 is a rear stage amplifier, 5 is an output terminal, 6 is a gate bias circuit, 7 is a GaAsFET
, 8 is a drain bias circuit, 9 is a gate current detection circuit, 10 is an external bias circuit, 11 is a voltage comparison circuit, 12
13 is a gate bias control circuit, 13 is a drain bias control circuit, and 14 is a power supply.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] GaAsFETを後端部に持つFET増幅器において、
後段増幅器のゲート端子に接続されたゲート電流検出回
路と、上記ゲート電流検出回路に接続したゲートバイア
ス制御回路及びドレインバイアス制御回路とを設けたこ
とを特徴とするFET増幅器。
In a FET amplifier with a GaAsFET at the rear end,
A FET amplifier comprising: a gate current detection circuit connected to a gate terminal of a rear-stage amplifier; and a gate bias control circuit and a drain bias control circuit connected to the gate current detection circuit.
JP16545883U 1983-10-26 1983-10-26 FET amplifier Pending JPS6074319U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16545883U JPS6074319U (en) 1983-10-26 1983-10-26 FET amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16545883U JPS6074319U (en) 1983-10-26 1983-10-26 FET amplifier

Publications (1)

Publication Number Publication Date
JPS6074319U true JPS6074319U (en) 1985-05-24

Family

ID=30362488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16545883U Pending JPS6074319U (en) 1983-10-26 1983-10-26 FET amplifier

Country Status (1)

Country Link
JP (1) JPS6074319U (en)

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