JPS6073722A - Control circuit of timer output - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a peripheral device, by inhibiting the propagation of an unnecessary signal generated and outputted before initialization from an LSI for timer control until the initialization is completed. CONSTITUTION:An FF14 and gate circuit 15 are added to the titled circuit. When the power is supplied to this system, a power-on clear signal is generated, and a microprocessor 11 and various logics are initialized based on the signal. When the FF14 is initialized under this conditon, the output of the FF14 is energizes the gate circuit 15 through a line 105 so as to inhibit sending out of a signal generated and outputted from an LSI12 for timer control. Since the propagation of an unnecessary signal from the LSI12 is inhibited, the malfunction of a peripheral device is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a timer output control circuit suitable for use in a computer system composed of a processor unit and peripheral devices.

[Technical background of the invention and its problems]

In recent years, advances in semiconductor technology have made it possible to construct computer systems with high performance by using a microprocessor as the core and connecting one peripheral device through several peripheral control LSIs.

One of the above-mentioned peripheral control LSIs is a programmable timer controller used for the purpose of adding counting and timer functions to a microprocessor serving as a control center. The microprocessor uses the signals generated by this timer control LSI as some control signals for peripheral devices connected to the system. The timer control LSI has an internal register and a counter, and implements a desired timer function by setting parameters such as an operation mode by a microprocessor.

By the way, 1. Usually, the above-mentioned timer control LSI does not have a power-on clear input like eight-doware. Therefore, initialization was also performed by setting parameters in the built-in registers.

Therefore, the timer control LSI may output an unnecessary uncertain signal before being initialized, which may interfere with the operation of peripheral devices connected to the system.

[Purpose of the invention]

The present invention has been made in view of the above drawbacks, and guarantees the operation of one peripheral device by prohibiting the propagation of unnecessary signals generated and output from a timer control LSI before initialization until the end of initialization. The purpose is to provide a timer output sub-axis circuit.

[Summary of the invention]

In order to achieve the above object, the present invention prohibits the sending of signals generated and output by the timer control LSI to peripheral devices until initialization parameter settings are completed in the register built into the timer control LSI. It is something.

For this reason, the power O generated when the system is powered on is
A flip-flop that performs 0N10FF based on the N clear signal and specific data set by the processor unit, and a gate that obtains a signal generated and output by the timer control LSI and prohibits signal transmission to peripheral devices based on the value indicated by the flip-flop. Added.

This eliminates the need to send a signal to one peripheral device before initialization (JSI for timer control), thereby preventing malfunctions of the peripheral device.

[Embodiments of the invention]

The configuration and operation of the embodiment of the present invention will be explained in detail below using one drawing.

For comparison, a conventional example is shown in FIG. 1, and an embodiment of the present invention is shown in FIG. 2. In the figure, 11 is a microprocessor serving as a control center, and 12 is a timer controller LSI that performs a predetermined timer count by setting parameters by this microprocessor 9''11.Generated by this timer count LS112. The output signal is sent to an external peripheral device (not shown) via the driver circuit 13.

In the embodiment of the present invention, a flip-flop 1 is added to the above configuration.
4. A gate circuit 15 is added.

The flip-flop 14 is supplied with a power ON clear signal generated when the system is powered on via a line 101, and specific data is supplied by the processor unit 11 via a line 102, and its output is sent via a line 105 to a gate circuit. 15 is supplied to one input terminal.

A signal generated and output by the timer controller L8Ix2 is supplied to the other input terminal of the gate circuit 15 via the line ZOS. The output of the gate circuit 15 subjected to the AND condition is sent to the driver circuit 13 . Connected via line 104 to one external peripheral device, not shown.

The operation of one embodiment of the present invention will be described in detail below.

First, when the system is powered on, a power ON clear signal is generated, and the microprocessor 11 and various logics are initialized based on this signal. Here, by initializing the flip-flop 14, its output energizes the gate circuit 15 via the line 105, so as to prohibit the sending of the signal generated and output by the timer control LSI x x. act. At the same time, the microprocessor ix is initialized, so that the firmware (the program executed by the microprocessor) is executed from an initial routine.

Normally, the initial routine of the firmware includes a routine for setting parameters for the register built into the timer control L8112, but it will take some time until this routine is executed. Therefore, during this time, the timer control LS
I12 generates signals unnecessary to the system.

It will end up being output. However, in the present invention, this signal is prohibited from being output by the gate circuit 15, so it is not sent to one peripheral device. Therefore, the operation of peripheral devices is guaranteed.

As the firmware initial routine processing (executed by the microprocessor 11) progresses, the timer control LS
When the initial setting of parameters for the register held by Ir2 is completed, unnecessary signals output from the timer control LSI 12 disappear. Thereafter, the microprocessor 11 follows the firmware and sets the flip-flop 14. As a result, the timer control LS112 output, which was previously prohibited by the gate circuit 15, is released, and the driver circuit 13
Send it to the peripheral device via .

Thereafter, in normal operation, the signals generated and output by the timer control L8IJJ are sent as they are to the peripheral devices, so that input/output operations can be performed normally.

Note that in the embodiment of the present invention, the timer control L
Although only the SI has been exemplified and the output signal is prohibited until it is initialized, the present invention can be applied to other ICs or LSIs that do not have hardware or rear inputs in a similar manner. It is applicable.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prohibit the propagation of unnecessary signals generated and output from the timer control LSI before initialization, and therefore it is possible to prevent malfunctions of peripheral devices caused by the above signals. , it is possible to provide a highly reliable computer system.

[Brief explanation of drawings]

Figure $1 is a conventional example, and Figure 2 is a block A showing an embodiment of the present invention. 11... Microprocessor, 12... LSI for timer control, zJ... Driver circuit. 14...Gate circuit, 15...Flip-flop. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] In a computer system consisting of a processor unit and peripheral devices, the processor unit sets parameters to control a timer control LSI that performs time counting, and the clear signal that arrives when the system is powered on and the identification by the processor unit. With the solitubflop that turns 0N10FF depending on the data setting and the output of this flipflop,
A timer output comprising: a gate circuit that prohibits sending out the signal generated and output by the timer control LSI; and a driver circuit that obtains the output of the gate circuit and sends the obtained signal to the peripheral device. control circuit.