JPH0149968B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer stop control method.

In recent years, as part of efforts to save energy in electronic devices, several methods have been attempted to reduce power consumption in microcomputer LSIs. One of them is the microcomputer.
A known method is to configure an LSI with CMOS and provide a HALT/STOP mode in which the clock supply to the CPU is stopped depending on the operating state. HALT here
The mode is to temporarily stop the supply of clock pulses to each part of the CPU except for specific circuits such as the interrupt detection part to cancel HALT mode.
STOP mode stops clock generation and
This control stops the clock supply to all the clocks.

A conventional stop control method will be explained using the block diagram of FIG.

Figure 1 shows the main parts of the instruction decoder.
and 5 are the HALT flag and
This is the STOP flag. 2 is an OR gate for resetting the HALT flag using an interrupt detection signal and a reset signal, and 3 is an interrupt detection circuit for detecting an interrupt request from an external interrupt input terminal 4.

In normal mode, the reset signal becomes active when the CPU starts operating, HALT flag 1 and STOP flag 5 are both reset, and the clock from the clock generator (not shown) is activated.
Supplied to various parts within the CPU.

After the interrupt enable flag (not shown) is activated by the program's interrupt enable instruction and an interrupt request can be detected through the external interrupt input terminal 4, the program's HALT instruction is decoded. Then, the HALT signal applied to the set terminal of RS-FF that constitutes HALT flag 1 becomes active level, and this HALT signal causes a gate circuit to inhibit the supply of clock pulses from the clock pulse generator to each part of the CPU. (not shown), the supply of clock pulses to each part of the CPU except the interrupt detection circuit 3 is stopped, and the state of each part is maintained.

Even when in HALT mode, the interrupt detection circuit 3 remains active, and when an interrupt factor occurs outside the CPU and an interrupt request signal is applied to the external interrupt input terminal 4, the HALT mode is released. An interrupt detection signal is generated for this purpose. The output of OR gate 2 is applied to the reset terminal of HALT flag 1, and in HALT mode, when the aforementioned interrupt request is detected and from the reset control terminal (not shown), the CPU
The configuration is such that the reset signal is released when a reset signal requesting a reset is issued.

On the other hand, STOP mode is a programmatic STOP mode.
STOP flag 5 configured as RS-FF by instruction
is set. STOP
When the signal goes to an active level, clock generation is stopped and all circuit operations are stopped while the internal state of the CPU is maintained. To cancel STOP mode,
This is accomplished only by resetting the CPU by applying an active signal to the reset control terminal.

Conventionally, as described above, by providing a HALT/STOP mode, the moving body of each part is stopped,
Although this technology saves power, the number of instructions required to execute these modes increases, and the hardware configuration for decoding the instructions becomes more complex. There is no program compatibility between the models and the hardware/software development support/
The problem was that the tools were complicated.

Therefore, the present invention aims to solve these problems, and the transition to HALT/STOP mode is performed using an interrupt wait instruction (Wait
Which mode the computer enters is determined by the control instructions for the interrupt enable flag, that is, the interrupt enable instruction (Interrupt Enable) and the all interrupt disable instruction (Interrupt Disable al). This paper proposes a stop control method. The present invention will be explained below using Examples.

The interrupt wait instruction (WI instruction) is an instruction that temporarily halts instruction execution. Instruction execution is resumed when an interrupt request is generated or a reset signal is input.

The interrupt enable instruction is an instruction that enables interrupt acceptance when an interrupt factor occurs.

The all interrupt disable instruction is an instruction that disables all interrupts even if an interrupt factor occurs, and instruction execution can only be resumed by inputting a reset signal.

The transition control to STOP mode and HALT mode is
Specify by a combination of interrupt enable instruction/all interrupt disable instruction and interrupt wait instruction.

To enter HALT mode, execute an interrupt wait instruction immediately after executing an interrupt enable instruction.

To enter STOP mode, execute the interrupt wait instruction immediately after executing the all interrupt disable instruction.

In other words, if any interrupt is enabled when an interrupt wait instruction is executed, instruction execution can be resumed by the interrupt, so the system enters HALT mode, and all interrupts are disabled when the interrupt wait instruction is executed. If it is, it will not be possible to resume instruction execution using an interrupt, so move to STOP mode.

FIG. 2 shows HALT and HALT of a microcomputer implementing the computer stop control method according to the present invention.
This shows the main parts of the STOP control circuit. In the figure, 11 and 15 are a HALT flag and a STOP flag respectively composed of RS-FF as in FIG. 1, 12 is an OR gate, 13 is an interrupt detection circuit, and 1
4 is an external interrupt input terminal, 16 is an AND circuit, 17
is the STOP detection circuit.

Operation in normal mode, HALT, STOP
The operation for canceling the mode is performed in the same manner as in the conventional example shown in FIG. That is, by activating the reset signal applied to one input terminal of the OR circuit 12 connected to the reset input terminal of the HALT flag 11 and the reset input terminal of the STOP flag 15, a transition to the normal operation mode is made. . The HALT mode is also released when an interrupt request is detected by the interrupt detection circuit 13.

When transitioning from normal operation mode to HALT mode, first, as preprocessing for transitioning to HALT mode, a program executes an interrupt enable instruction to set an interrupt enable flag (not shown).
A state is made in which an interrupt request can be input through the external interrupt input terminal 14, and the interrupt wait signal (WI signal) is made active by executing the subsequent interrupt wait instruction, and the HALT flag 11 is set. . As a result, the HALT signal becomes active, and as in FIG. 1, the clock supply to circuits other than the specific circuits necessary to release the HALT mode, such as the interrupt detection circuit 13, is stopped. The WI signal is also supplied to one input terminal of the AND gate 16 connected to the set input terminal of the STOP flag 15.
The other input terminal of the AND gate 16 is connected to the output terminal of the STOP detection circuit 17, and since the output of the STOP detection circuit 17 becomes an active level only when an interrupt disable instruction is executed, the STOP flag 15 remains in the reset state.

Next, when transitioning from the normal operation mode to the STOP mode, first, as preprocessing for transitioning to the STOP mode, an interrupt disable instruction is executed to reset the interrupt enable flag for disabling all interrupts. As a result, the application of an interrupt request to the interrupt input terminal 14 is prohibited, and the STOP detection circuit 1
7 output becomes active level. When the interrupt standby instruction is executed in this state, the STOP flag 15 is set together with the HALT flag 11, and the STOP signal goes to the active level, so that the stop control is performed by clock generation as in Fig. 1. . here,
The HALT signal also becomes active level at the same time,
Since clock generation is stopped by the STOP signal, there is virtually no change.

In this embodiment, the interrupt enable instruction, interrupt wait instruction, and all interrupt disable instruction are all HALT/
The present invention is characterized by the fact that these instructions are the same as those used in conventional microcomputers that do not have a STOP mode, and the combination of these instructions controls transition to HALT and STOP modes. That is, as described in the conventional example, by adding the HALT/STOP mode, there is no need to prepare separate instructions for transitioning to each mode and to provide a decoder to decode those instructions. Therefore, the hardware configuration does not become complicated.
In addition, the development support tools for microcomputer hardware and software are HALT/
It has the advantage that it can be used in common with conventional models that do not have a STOP mode.

As is clear from the above explanation, the computer stop control method according to the present invention is achieved by executing an interrupt wait instruction after executing an interrupt enable instruction.
It is possible to transition to HALT mode and execute the interrupt wait instruction after executing the all interrupt disable instruction to transition to STOP mode.
This has excellent effects such as making it possible to share software with conventional models that do not have a STOP mode.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional computer stop control method, and FIG. 2 is a main part block diagram of a device to which the computer stop control method according to the present invention is applied. 11...HALT flag, 12...OR gate, 13
...Interrupt detection circuit, 14...Interrupt input terminal, 15...
STOP flag, 16...AND gate, 17...
STOP detection circuit.

Claims (1)

[Claims] 1 HALT, which temporarily stops clock supply to each part of the CPU except for the circuit that cancels HALT mode
A signal that becomes active when the interrupt wait instruction is executed is added to the set input side of the flag, and a signal that becomes active when the interrupt disable instruction is executed is added to the set input side of the STOP flag that controls clock generation. and a signal that becomes active upon execution of the interrupt standby instruction, and the HALT flag or STOP is set as
A computer stop control method characterized in that a flag is set.