JPH03148731A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To decrease malfunction to suddenly stop source oscillation by providing a means to select whether an instruction procedure to stop the source oscillation is made valid or invalid. CONSTITUTION:A flip-flop 10 holds setting whether a stop instruction to stop the oscillator of a clock generation part 3 and to stop a clock is made valid or invalid. In the case of an operation to use the STOP instruction, just after a single chip microcomputer 1 is reset, the first instruction to be executed by a CPU 4 is defined as an instruction for making the STOP instruction valid. When the STOP instruction is turned to an invalid state after resetting the single chip microcomputer 1, the clock is not stopped even in case the CPU 4 fetches the STOP instruction by the run away, etc., of the CPU 4. Thus, it can be decreased that the source oscillation is suddenly stopped by the malfunction, etc., and a normal operation can not be recovered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a single-chip microcomputer.

[Prior Art J] Figure 6 is a block diagram of a conventional single-chip microcomputer. (6) is ROM.

<6) LtRAM, cn data 7g timer, (8
) is a flip-flop that holds the setting for enabling or disabling the watchdog timer (2), and (9) is an external interrupt input terminal.

Next, the operation will be explained.

After resetting the single-chip microcomputer (1), the CPU (4) reads programs from the ROM (ω) and executes them sequentially. At this time, each operation inside the single-chip microcomputer (1) is controlled by the clock generator Note that the clock generator (3) is mainly composed of an oscillator using a resonator.The CPU (4) runs in synchronization with the clock signal generated in step (3). 3) Command to stop the oscillator (STO
P), an instruction to enable the watchdog timer (
VDT-E), watchdog timer (instruction to disable η (VDT-D), watchdog timer (7)
has an instruction (W-DT-CLR) to instruct timer clear.

In the case of a single-chip microcomputer that uses a watchdog timer, after reset, the CPU (4)
Execute the DT-H command and enable the watchdog timer (?) by setting the flipflop (81). When a certain value is reached, the system is considered abnormal and the single-chip microcomputer (1) is re-centered.
Place VDT-CLR instructions at appropriate locations in the program (by clearing the watchdog timer (7) before the watchdog timer (η) resets the single-chip microcomputer (1)). If the count value is returned to the initial value by performing Dog timer (VDT-C before the count value of 1 reaches the specified value)
If the LR instruction is not executed, the watchdog timer (7) is activated by the single-chip microcomputer (1).
Perform a reset.

Then restart the execution from the beginning.

In addition, when using the STOP instruction, after the STOP instruction is executed, an interrupt request signal arrives at the external interrupt input terminal (9), and the oscillator of the clock generator (3) resumes oscillation, and the clock supply is resumed. watchdog timer (
The counting operation in 7) is stopped.

Note that in the case of a one-chip microcomputer that does not use the function of the watchdog timer I''I), the WDT-D instruction may be executed in advance.

[Invention tries to solve it! I! If) Conventional single-chip microcomputers were configured as described above, so the contents of the flip-flop that holds the enable/disable setting of the watchdog timer may be rewritten and become invalid due to external noise or other reasons. ,In application, ST
Even though the OP instruction is never used, if the STOP instruction is executed due to a malfunction, the watchdog timer also stops and cannot return to normal operation.

This invention was made to solve the above-mentioned problems, and the first invention is a single-chip microcomputer that is less likely to fall into a state where the source oscillation stops unexpectedly due to malfunction or the like and cannot return to normal operation. The purpose is to obtain.

A further object of the second invention is to provide a single-chip microcomputer that is unlikely to fall into a state where the watchdog timer itself becomes invalid due to malfunction and no longer detects malfunction.

[Means to solve the problem]

The single-chip microcomputer according to the first invention makes the STOP instruction valid only when the CPU performs a predetermined procedure under certain special conditions, and makes the STOP instruction invalid almost at any time. A mechanism is provided to accept commands to do so.

Furthermore, the single-chip microcomputer according to the second invention disables the watchdog timer only when the CPU performs a certain special procedure, and enables the watchdog timer almost at all times. A mechanism is provided to accept commands to do so.

(Operation) Since the single-chip microcomputer according to the first invention has a constraint condition for executing the STOP instruction, the single-chip microcomputer does not stop even if the STOP instruction is encountered unless the condition is met.

In the single-chip microcomputer according to the second aspect of the invention, the watchdog timer is not disabled if the conditions are not met because a constraint is provided to disable the watchdog timer.

〔Example〕

Below, the first, second... An embodiment of the third invention will be described with reference to the drawings. In FIG. 1, (υ) is a single-chip microcomputer, (W) is a bus, (3) is a clock generator including a source oscillation circuit, and (A) is a CPU.

(5) is the ROM, (6) is the ROM% (7) is the watchdog timer, (Sushi is a flip-floor probe that holds the setting for enabling or disabling the watchdog timer (7), (9) is an external input, a terminal, and (to) is a flip floor that holds the setting to enable or disable the command to stop source oscillation and clearing.

Figure 2 is an example of a slightly more detailed block diagram around the flip-flop side. aD is the first instruction detection circuit that detects whether it is the first instruction immediately after re-cent, (b) is the SYNC signal input section, a1 is the reset signal input section, and trout is the detection output of the first instruction. A hail DE
This is a T signal output section.

Next, the operation will be explained. Single-chip microcomputer (1) After centrifugation, c P U <a is R
The program is read from the OM (5) and executed one after another. At this time, each operation inside the single-chip microcomputer (1) proceeds based on the clock signal generated by the clock generator (j). go.

c p U (4) is a command STOP%STO to stop the oscillator of the clock generator (3) and stop the clock.
Instruction STOP-E to enable the P instruction, instruction STOP-D to disable it, watchdog timer (7
) instruction VDT-E to enable, instruction VDT-D to disable watchdog timer (7), instruction VDT-CL to instruct watchdog timer (7) to clear the timer.
I have R.

In the case of an operation using the STOP instruction, as shown in FIG.
If you set it to OP-E, then when you execute the STOP command from now on, the oscillation will stop and the clock will stop.

In addition, in the case of operation that does not use the STOP command, after resetting the single-chip microcomputer (1), 810
P command 1 invalid state 9″-74! O?・lCP U (
The clock does not stop even if CPU (4) fetches the STOP instruction due to a runaway in CPU (4).
The P-E instruction means that bits 3 to 0 are 1110 (2
This is an i instruction that performs a function of writing a value such as The SYNC signal that is manually input to the SYNC input section is a signal that generates one pulse every time the CPU (shoulder) enters the instruction reading state.The RESlt signal that is manually input to the reset signal input section is a single-chip signal. This signal indicates that the microcomputer is in the reset state.The WR signal indicates that the CPU (4) is outputting a certain address to the address bus and certain data to the data bus. This is a signal indicating that a write operation is in progress.

The first instruction detection circuit aυ wanders so that 1 is output from the DET signal output section only during the first instruction after reset, and when reading the second instruction, the DET signal output section
The signal becomes O. In addition, count input to the internal counter is prohibited, and SYNC is disabled unless the RES signal is received.
Since no signal is received, the signal value of the output section remains O no matter how many commands are received thereafter.

Further, when the Q output of the RS flip-flop (to) which sets whether to enable or disable the STOP instruction is 1, the STOP instruction becomes invalid when the STOP instruction valid Q output is O. Therefore, if the first instruction immediately after reset is the above-mentioned STOP-E instruction, the RS flip floor block a
A pulse of 1 enters the S input of ・, the Q output becomes 1, and the S
The TOP command becomes valid. If the STOP-F command is not executed after reset, the Q output becomes O due to the l pulse input to the R input of the RS flip floor probe (2) at the time of reset, and the STOP command is invalid. Also, first ST
If the OP-E command is not executed, logically the Q output cannot be set to 1 unless a reset is input thereafter. However, if it becomes 1 due to noise malfunction etc., the method to return it to 0 is as follows: Bit 3 to bit 0 is 1110
There is an operation to write a value other than (binary) to the REGADR address. This corresponds to the STOP-D command mentioned above. ST
In an operation that does not use an OP instruction, the possibility that the clock will stop is reduced by inserting STOP-D instructions here and there in the program, as shown in an example in FIG.

Next, an embodiment of the second invention will be described using FIG. 1 and FIG. 3. FIG. 3 is an example of a somewhat detailed block diagram around the Friab flop (8).
8) is the watchdog timer (71 latl?.

This is an RS flip-flop for setting whether to enable or disable. When the Q output of this RS Friab flop (8) is 1, the function of the watchdog timer (η) is enabled; when the Q output is 0, the function of the watchdog timer [7] is disabled. Single-chip microcomputer (1) is reset, the RS Friab flop (
Since a signal of 1 is input to the S input of 8), the Q output becomes 1, and the watchdog timer (sword) function is enabled.
In the first instruction immediately after reset when the T signal becomes 1, it is necessary to write the value of bit full bit 4 of 1101 (binary) to the REGADR address. The aforementioned VDT-
The D command performs this operation. If the VDT-D command is not executed immediately after reset, the Q output of the Friab flop (8) will be 1 as described above, and logically, unless a reset is input thereafter, the Q output cannot be set to 0. The function of watchdog timer Cη remains valid. However, if it becomes O due to a noise malfunction, etc., the way to return it to 1 is to set Bitfull Bift 4 to 1101 (2
There is an operation to write a value other than (address) to the REGADR address. This corresponds to the above-mentioned WDT-E command. For applications that use the watchdog timer (7) function, VDT-E
By inserting instructions here and there in the program, the possibility that the function of the watchdog timer (7) remains disabled is reduced.

In the above embodiment, the first invention and the second invention were explained independently, but by combining them, it is possible to obtain four variations such as STOP enabled and watchdog disabled, STOP disabled and watched, and watchdog enabled. can.

Furthermore, in the above embodiment, only the point that Kurofuku does not stop when the STOP command is executed when the STOP command is invalid has been mentioned, but it may be processed in the same way as the execution of an illegal command. Processing may be performed.

In addition, in the above embodiment, under limited conditions, that is, other than the instruction immediately after reset, the STOP instruction or the watched instruction,
If you enable/disable the timer or attempt to switch it, the intended operation will be executed, but if you try to change it outside of the limited conditions, an illegal instruction will be executed or a reset will occur. Processing such as causing an action may also be performed.

Further, in the above embodiment, the instruction procedure for setting the STOP instruction or the validity/invalidity of the watchdog timer is a simple one requiring only one instruction, but it may be more complicated.

Furthermore, in the above embodiment, enabling/disabling of the STOP instruction and enabling/disabling of the watchdog timer are set independently, but by sharing the FRIAB flop for setting, the STOP instruction is enabled and the watchdog timer is disabled. and ST
Two states may be selected, such as OP instruction disabled and watched, and watch timer enabled.

In addition, in the above embodiment, there is one FLAB flop each for setting the enable/disable of the STOP instruction and the enable/disable of the watchdog timer.
Two or more flip-flops for invalid setting are provided, and STOP is true only when all flip-flops are STOP enabled.
The configuration may be such that TOP is enabled.

Further, although the actual state of the STOP instruction is not clear in the above embodiment, it may be an inherence instruction, an instruction to access a certain address, or even a collection of smaller instructions. good.

〔Effect of the invention〕

As described above, according to the first invention, a means is provided for selecting whether to enable or disable the command procedure for stopping source oscillation, and in particular, a condition under which the enabling procedure can be performed is provided. Since this is limited, malfunctions in which the source oscillation is inadvertently stopped are reduced, especially in operations where the source oscillation is used without stopping.

Therefore, if you provide a software-based means of returning to normality, the probability of a normal recovery will increase, and if you have a clock-counting watchdog timer, the probability that this watchdog timer will work effectively will increase. Therefore, a highly secure single-chip microcomputer can be obtained.

Furthermore, according to the second invention, the conditions under which the watchdog timer can be disabled are limited, especially in operations that use the watchdog timer, so that runaway C
Even if the PU attempts to execute an instruction procedure to disable the watchdog timer, the watchdog timer will not be disabled, resulting in a highly secure single-chip microcomputer.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a single-chip microcomputer according to an embodiment of the present invention, and Fig. 2 shows whether to enable or disable the instruction to stop source oscillation and stop the clock in an embodiment of the present invention. FIG. 3 is a somewhat detailed block diagram of the fritub flop (to) that holds the settings for the watchdog timer in one embodiment of the present invention. 4 is a flowchart of software that stops source oscillation according to an embodiment of the present invention, and FIG. 5 is a flowchart of software that does not stop source oscillation according to an embodiment of this invention. Figure 6 is a block diagram of a conventional single-chip microcomputer. In the figure, (l) is a single chip micro combinator, (c) is a bus, (3) is a clock generator, and (4) is a block diagram of a conventional single-chip microcomputer.
is a CPU, (5) is a ROM, (6) is a RAM, (7) is a watchdog timer, (8) is a flip-flop that holds the enable/disable setting of the watchdog timer, (9)
is an external interrupt input terminal, the side is a flipflop that holds the setting to enable or disable the instruction to stop the source oscillation and stop the clock, I is the first instruction detection circuit, (2
) is the SYNC signal input section, I is the reset signal input section, α
The symbol indicates the DET signal output section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a single-chip microcomputer,
means for enabling a command procedure to stop source oscillation only when a predetermined command procedure is executed under certain limited conditions; A single-chip microcomputer comprising means for invalidating the instruction to stop source oscillation when executed. (2) In a single-chip microcomputer,
means for disabling the watchdog timer only when a predetermined command procedure is executed under certain limited conditions; The single-chip microcomputer described above has means for enabling a watchdog timer.