JPS6073572A - Memory control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory control method suitable for use in graphic processing and image processing systems.

[Technical background of the invention and its problems]

The need for graphic processing and image processing using computers is increasing. Computers that support graphic processing and image processing have a bitmap memory that corresponds to the display surface and dots as display memory, and the bitmap memory usually has multiple planes to represent display attributes in addition to display data. is provided. However, this memory plane with no display attributes is not necessarily used all the time, and therefore there is a lot of waste from the viewpoint of memory usage.

By the way, when moving the data developed on the above bitmap memory on the display screen by scrolling, etc.
Re-developing the data each time causes a decrease in processing speed. In reality, it uses a bitmap memory larger than the display screen size to expand the data, and uses a window viewport conversion function that moves the display area on top of it to prevent a drop in processing speed. However, having a larger bitmap memory requires multiple use of memory elements, making the computer system itself expensive.

It had the disadvantage of being large in size.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and in addition to using the plane for display attributes as a memory that does not realize the original function, the present invention uses R6ad as an independent memory plane.
It is an object of the present invention to provide a memory control system that effectively utilizes a bitmap memory whose size is limited by operating in a Jrite-enabled mode and specifying this mode switching using an address map memory.

[Summary of the invention]

In order to achieve the above object, the present invention provides an address map memory having the table configuration shown below in the front stage of a plurality of bitmap memory planes in which display data and its display attributes are stored in the form of bitmap images. One entry in address memory can be used for either using the memory plane for which the display attribute is set for its original purpose, or for reading/writing as an independent plane memory.
an access mode specification section in which it is set whether to access the memory as a memory that can be accessed; an information section in which selection information for that memory grain is set when the latter mode is set; and display data developed on the bitmap memory It consists of an address information section that maps the information on the actual display screen.

At the display timing, the display controller refers to the address map memory, decodes the contents of the mode setting section, and when a certain mode is indicated, selects a bitmap corresponding to the address indicated by the address information in the plane indicated by the plane selection information section. The pixel information of the memory is displayed on the CRT monitor, and when another mode is indicated, the pixel information of the bitmap memory corresponding to the address indicated in the address information section is modified and displayed.

As a result, the plane for display attributes can be used effectively, display data can be developed over a wider range than in the past, and the processing speed of scrolling and the like is improved.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a graphic processing system to which the present invention is applied.

In the figure, 11 is the CPU, z2 is the main memory (MMU)
It is. Programs and data are stored in the main memory 12, and the CPU II performs data processing based on the programs. 13,14.

15 is bit map memory (BMM).

The data to be displayed on the CRT monitor 19 is stored in the bitmap memory 13 in the form of a bitmap image (in a format developed into dots). Further, the bitmap memory 14 is originally stored as a bitmap image showing the attribute of high brightness display, and the bitmap memory 15 is originally stored as a bitmap image showing the attribute of blinking display. Further, in the present invention, the bitmap memo IJ4, Js is used as an independent plain memory that can be read/written depending on the mode, as described above.

17 is an address map memory (AMM). The address map memory 17 is
This is a memory that stores a table that divides the data addressed in the -Y direction into both types of information and maps the data developed on the bitmap memory 13 onto the actual display screen. Figure 2 shows a development diagram of Jfi ability. In the present invention,
The following data is further added to this address map memory 17. That is, one is a mode setting section.

In the present invention, the plane for display attributes is also used as an independent memory for reading/vV of information in contrast to the bitmap memory.
There are two modes (7): a mode in which the r ite is possible (hereinafter referred to as "all mode") and a mode in which parallel processing is performed as a conventional display attribute plane (hereinafter referred to as "split mode"). did. MSB 1 of the entry configuring the table for this mote switching
Specify in bits. The other one is a plane selection information section. In this information section, plane selection information of the bitmap memory is set in the all mode, and is not used in the split mode.

FIG. 3 shows the format of entries constituting the table of the address map memory 17. The mode setting section is M, the rune selection information section is SEL, and the address information section is X-ADR.

It is indicated as Y-ADR. Returning the explanation to Figure 1, 18
is a display controller (CRTC).

The display controller 18 interfaces the CPUJJ and the raster scan type CRT monitor I9,
In addition to generating various control signals for display based on the parameters set by C and PUll, the mode setting section M of the address map memory 17 cooperates with the CPU.
, and control the display according to that mode. 19 is a CRT monitor.

Above CPUJ J, main memory 12, display controller 1
8, address map memory 17, and bit map memories 13, 14, and 15 are commonly connected to system path 16.

The operation of the embodiment of the present invention will be described in detail below.

Main memory 12 contains programs and display data to be executed by the system. Before the display data is displayed on the CRT monitor 19, it passes through the main memory 12 color system path 16 and is expanded dot by dot in the pit mass memories 13, 14 and 15 under the control of the CPUJz. . The address map memory 17 also has bit map memories J3, 14.15 in advance.
Information indicating which pixel information is to be displayed on the CRT monitor 19 is input to the main memory 12 in the format shown in FIG.

Now, when the CPUJl accesses the display ON command according to the program stored in the main memory 12, the display controller 18 starts full operation, sequentially analyzes the information in the address map memory 17, and
, 14.degree. 15 is displayed on the CRT monitor 19.

Here, as shown in FIG. 3, if the MSB of the address map memory 17 specifies all mode, the bit map memories 13, 14 and 15 each function as an independent memory plane, and the plane selection information Department (
3EL) specified memory plane (J s, J
4, J5), pixel information of the address indicated by the X direction and Y direction address information (ADR)
It is displayed on the RT monitor 19. On the other hand, the address map
If the contents of the MSB of the memory 17 specify the split mode, the bitmap memories 14 and 15 perform their original function as the display attribute memory of the plain memory 13, and store the bitmap memory's X and Y direction address information ( A.D.
CRT monitor 1 by modifying the address pixel information indicated by
Display on 9.

Although the embodiments of the present invention have been described with reference to a CRT display device, the invention is not limited to this, and the same method can be applied to the printing memory of a page printer used in a graphic processing or image processing system. It can be applied.

〔Effect of the invention〕

As explained above, according to the present invention, by switching the access mode of the bitmap memory in the address map memory, when the plane for display attributes is not used, the plane can be used as an independent memory, which can be used over a wide range of areas. It is possible to develop various data on the bitmap memory at one time, and furthermore, it is possible to obtain the effects listed below.

(1) By using the all mode, display data can be expanded over a wider range than before, and the processing speed of scrolling etc. is improved.

(2) Conventionally, the memory plane for display attributes was not used at all when displaying screen decorations, but it can be used effectively by using it as an independent plane memory in all modes.

I can do that.

(3) By effectively using the bitmap memory, a conventional system does not require a memory element, making it possible to use a small and inexpensive system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a graphic processing system to which the present invention is adopted, and FIG. 2 is a functional development diagram showing the correspondence between the bitmap memory address map memory and the display screen shown in FIG. , FIG. 3 is a diagram showing the data format of each entry constituting the address map memory. 11...CPU, I,? ...Main memory, 13, 1
．． 4. 15... Bit mass memory, 17... Address map memory, 18... Display controller, 19...
CRT monitor. Applicant's agent Patent attorney Takeshi Suzue Model box 1 Figure 3

Claims (1)

[Scope of Claims] A bitmap memory having a multi-plane configuration in which display data and data indicating the display attributes of each display data are developed and stored in a processor unit pixel by pixel, and at least access to the bitmap memory. mode, and memory above. an address map memory having a table structure in which one entry is composed of program selection information and address information obtained by mapping the display data developed on the bit map memory onto the actual display screen; and parameters by the processor unit. The display controller includes a display controller that generates various control signals in order to obtain data from the bitmap memory via the address map memory and display desired data on the display screen based on the settings, and the display controller receives the data from the bitmap memory via the address map memory. Refers to the address map memory, and when a certain access mode is set, the memory plane specified in the plane selection information field of that entry. The pixel information of the address indicated by the address information field is displayed on the display screen, and if another mode is set, the pixel information of the bitmap memory corresponding to the address indicated by the address information field is modified and displayed. A memory control method characterized by