JPS6070721A - Laterally epitaxial growth - Google Patents

Laterally epitaxial growth

Info

Publication number
JPS6070721A
JPS6070721A JP58176902A JP17690283A JPS6070721A JP S6070721 A JPS6070721 A JP S6070721A JP 58176902 A JP58176902 A JP 58176902A JP 17690283 A JP17690283 A JP 17690283A JP S6070721 A JPS6070721 A JP S6070721A
Authority
JP
Japan
Prior art keywords
sio2
regions
single crystal
region
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58176902A
Other languages
Japanese (ja)
Other versions
JPH0377654B2 (en
Inventor
Junji Sakurai
桜井　潤治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58176902A priority Critical patent/JPS6070721A/en
Publication of JPS6070721A publication Critical patent/JPS6070721A/en
Publication of JPH0377654B2 publication Critical patent/JPH0377654B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To check drifting of an insulating region processed by laser annealing, and to enable to form the SiO2 region at a scheduled position by a method wherein insulating regions of the plural number on a semiconductor substrate are conected by connecting bridges. CONSTITUTION:Three rectangular SiO2 regions (islands) 12 and connecting bridges 14 consisting of SiO2, for example, to connect the three SiO2 regions 12 thereof are formed at the same time according to patterning on a single crystal silicon substrate 11. A polycrystalline silicon layer is formed according to the CVD method on the SiO2 regions 12 having the connecting bridges 14 consisting of SiO2 like this, and when annealing is performed using continuously oscillating argon laser as usual from the periphery of the SiO2 region to make the polycrystalline silicon layer to grow laterally epitaxially to be converted into a single crystal, even when the single crystal silicon substrate 11 is molten according to laser annealing to make the SiO2 region 12 under the polycrystalline silicon layer to be annealed to be in a drifting condition, movement thereof is controlled according to the connecting bridges connected to the unirradiated other two SiO2 regions, and to check drifting of the SiO2 region can be attained.

Description

【発明の詳細な説明】 発明の技術分野 本発明はラテラルエピタキシャル成長方法に係り、特に
ビームアニールによるラテラルエピタキシャル成長方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a lateral epitaxial growth method, and more particularly to a lateral epitaxial growth method using beam annealing.

技術の背景 単結晶基板上に堆積させた非単結晶層１例えば多結晶シ
リコン層にレーザービーム、電子ビーム。Background of the Technology A non-single-crystalline layer 1, for example a polycrystalline silicon layer, deposited on a single-crystalline substrate is treated with a laser beam or an electron beam.

イオンビーム等のエネルギビームＱｌ照射することによ
って横方向にエピタキシャル成長（ラテラルエピタキシ
ャル成長、以下単にＬＥＧと記す）全行ない該多結晶シ
リコン全基板単結晶と同一結晶方位のシリコンに単結晶
化せしめる方法が知られている。特に数ミリ角以上の大
面積のシリコン層を完全に単結晶化することは結晶粒界
や結晶転移の発生のために容易ではない。There is a known method of performing lateral epitaxial growth (hereinafter simply referred to as LEG) by irradiating the polycrystalline silicon with an energy beam Ql such as an ion beam to form a single crystal of silicon having the same crystal orientation as the single crystal of the entire polycrystalline silicon substrate. ing. In particular, it is not easy to completely monocrystallize a silicon layer with a large area of several millimeters square or more because of the occurrence of crystal grain boundaries and crystal dislocations.

従来技術と問題点 上記のように大きな面積部分のシリコン層全単結晶化す
ることが出来ないため、従来Ｄｅｖｉｃｅ領域等の孤立
した各々数十ミクロン角〜数百ミクロン角程度の小面積
のみＱ　Ｓｏｌ領域（５ｉｌｉｃｏｎＯｎ　Ｉｎ５ｕｌ
ａｔｏｒ　）として、その周囲の単結晶シリコン層を単
結晶化の種結晶にすることが行なわれている。第１図に
は単結晶シリコン層１上にデバイス領域となる３つの５
ｉ０２領域２が示されている。第２図には第１図のＡ−
Ａ断面図が示されている。Prior Art and Problems As mentioned above, it is not possible to completely single-crystallize a silicon layer in a large area, so conventionally Q Sol is applied only to isolated small areas such as device regions, each several tens of microns square to several hundred microns square. Area (5iliconOn In5ul
Ator), the surrounding single crystal silicon layer is used as a seed crystal for single crystallization. Figure 1 shows three 5
i02 area 2 is shown. Figure 2 shows A- in Figure 1.
A sectional view is shown.

嬉１．第２図に示されているような配置においてレーザ
ーアニール（スキャニング方向をＢとする）によって５
ｉ０２領域２上に形成した多結晶シリコン層３を単結晶
化する場合（第２図中１°ａは多結晶シリコン層３を単
結晶化するための種結晶部）、該レーザーアニールによ
り充分に単結晶シリコン基板１が加熱溶融されると第３
図に示すように溶融シリコンの融液の中で５ｉｎ２領域
２が元の位置２ａから多くの場合スキャニング方向のあ
る位置２ｂに漂流し、予定した位置にＳｏｌ領域全形成
することが出来ないことがしばしば発生した。Happy 1. 5 by laser annealing (scanning direction B) in the arrangement shown in Figure 2.
When the polycrystalline silicon layer 3 formed on the i02 region 2 is to be made into a single crystal (1°a in FIG. 2 is a seed crystal portion for making the polycrystalline silicon layer 3 into a single crystal), the laser annealing is sufficient. When the single crystal silicon substrate 1 is heated and melted, the third
As shown in the figure, in many cases, the 5in2 region 2 drifts from the original position 2a to a certain position 2b in the scanning direction in the molten silicon, making it impossible to form the entire Sol region at the planned position. occurred often.

発明の目的 上記欠点を鑑み本発明は予定された位置にＳｏｌ領域を
形成することが可能なラテラルエピタキシャル成長方法
全提供することである。OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention provides a complete lateral epitaxial growth method capable of forming Sol regions at predetermined locations.

発明の構成 本発明は半導体基板上に複数の絶縁領域全形成し５該絶
縁層上を含む部分に非単結晶層を形成し。Structure of the Invention In the present invention, a plurality of insulating regions are all formed on a semiconductor substrate, and a non-single crystal layer is formed in a portion including the top of the insulating layer.

次に該非単結晶層にエネルギーブームを照射して該非単
結晶層全単結晶化せしめるラテラルエビタ　−キシャル
成長方法において前記複数の絶縁領域の各々が他の絶縁
領域に対して相互に連結手段を有するように前記複数の
絶縁領域を形成することを特徴とするラテラルエピタキ
シャル成長方法によって達成される、 本発明において上記の連結手段は少なくとも半導体基板
の融点において、溶融せず且つ変形しない物質例えばＳ
　ｉ０２　、　Ｓ　ｉ　３Ｎ４等から作られるのが好ま
しい。Next, in the lateral epitaxy growth method in which the non-single crystal layer is irradiated with an energy boom to make all of the non-single crystal layer single crystal, each of the plurality of insulating regions has means for interconnecting with other insulating regions. In the present invention, the connecting means is made of a material that does not melt or deform at least at the melting point of the semiconductor substrate, such as S.
Preferably, it is made from i02, S i 3N4, etc.

発明の実施例 以下本発明の実施例全図面に基づいて説明する。Examples of the invention Embodiments of the present invention will be described below based on all the drawings.

第４図は本発明の１実施例會示す概略平面図である。FIG. 4 is a schematic plan view showing one embodiment of the present invention.

第４図に示すように例えば単結晶シリコン基板１１上に
３つの矩形状のＳｉ０ｇ領域（島）１２及びその３つの
８ｉ０２領域１２ｔ一連結する例えば８　ｉ　０２から
なる連結橋１４がバターニングによって同時に形成され
ている。この３つ連結橋１４の幅は５ｉ０２領域１２の
各辺の長さの約４゜の長さであるのが好ましい。という
のは５ｉ０２領域周辺の該基板１１が単結晶化の種とな
るために、該連結橋がシリコンの融点温度で変形しない
程度に出来るぞけ、連結橋の幅全細くすべきだからであ
る。As shown in FIG. 4, for example, three rectangular Si0g regions (islands) 12 and their three 8i02 regions 12t are connected together on a connecting bridge 14 consisting of, for example, 8i02, on a single crystal silicon substrate 11, simultaneously by patterning. It is formed. Preferably, the width of the three-piece connecting bridge 14 is approximately 4° the length of each side of the 5i02 region 12. This is because the substrate 11 around the 5i02 region serves as a seed for single crystallization, so the width of the connecting bridge should be made narrow in its entirety so that it can be formed to such an extent that it does not deform at the melting point temperature of silicon.

このようにして５ｉ０２からなる連結橋１４を有した５
ｉｎ２領域１２上方にＯＶＤ法によって多結晶シリコン
層（図示せず）を形成し、５ｉｎ２領域周辺から従来通
り連続発振アルゴンレーザ全円いてアニールを行ない多
結晶シリコン層をラテラルエピタキシャル成長させ単結
晶化せしめた。該レーザアニールによって単結晶シリコ
ン基板１１が溶融して被アニール多結晶シリコン層下の
５ｉＯｚ領域１２が浮遊状態になったとしても照射され
ていない他の２つのＳｉ０ｇ領域に連結された連結橋に
よって動き全抑制さｎ　Ｓ　ｉ　０２領域の漂流全防止
　□することが可能となる。この実施例ではＳ　ｉ　０
２領域は同形の矩形で短辺８ｏμｍ、長辺１’００μｍ
　の長さを有するように形成したので連結橋の幅を２μ
ｍ〜５μＩｎの長さに形成した。In this way, the 5
A polycrystalline silicon layer (not shown) was formed above the 5in2 region 12 by the OVD method, and annealing was performed using a continuous wave argon laser in the entire circle from around the 5in2 region in the conventional manner to cause lateral epitaxial growth of the polycrystalline silicon layer to form a single crystal. . Even if the single crystal silicon substrate 11 is melted by the laser annealing and the 5iOz region 12 under the annealed polycrystalline silicon layer becomes a floating state, it will move due to the connecting bridge connected to the other two Si0g regions that are not irradiated. It becomes possible to completely prevent drifting in the n S i 02 area. In this example, S i 0
The two areas are identical rectangles with short sides of 8oμm and long sides of 1'00μm.
Since it was formed to have a length of , the width of the connecting bridge was 2μ
It was formed to have a length of m to 5 μIn.

本発明の実施例においてアルゴンレーザビームを用いて
アニールを行なったが電子ビーム、イオンビーム、ラン
プ（放電、タングステンランプ）等の種々のエネルギー
ビームを用いても同様に行なうことが出来る。Although an argon laser beam was used for annealing in the embodiments of the present invention, the annealing can be similarly performed using various energy beams such as an electron beam, ion beam, lamp (discharge, tungsten lamp), etc.

発明の詳細 な説明したように本発明によれば予定された位置に８０
Ｉ領域を形成することが出来る。According to the present invention, as described in detail, 80
An I region can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図から第３図迄は従来技術を説明するための図であ
り、第４図は本発明の１実施例を説明するための概略平
面図である。 １．１１・・・単結晶シリコン基板。 ２．１２・・・８ｉ０２領域（島）。 ３・・・多結晶シリコン層。 １４・・・連結橋（”５ｉ０２）。 第１図 第２図 第３図 第４図1 to 3 are diagrams for explaining the prior art, and FIG. 4 is a schematic plan view for explaining one embodiment of the present invention. 1.11...Single crystal silicon substrate. 2.12...8i02 area (island). 3... Polycrystalline silicon layer. 14... Connecting bridge ("5i02). Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 １、半導体基板上に複数の絶縁領域を形成し。 該絶縁層上を含む部分に非単結晶層を形成し１次に該非
単結晶層にエネルギービームを照射して該非単結晶化せ
しめるラテラルエピタキシャル成長方法において。 前記複数の絶縁領域の各々が他の絶縁領域に対して相互
に連結手段全有するように前記複数の絶縁領域を形成す
ることを特徴とするラテラルエピタキシャル成長方法。 ２、前記連結手段に少なくとも前記半導体基板の融点に
おいて溶融せず且つ変形しない物質からなることを特徴
とする特許請求の範囲第１項記載のラテラルエピタキシ
ャル成長方法。[Claims] 1. A plurality of insulating regions are formed on a semiconductor substrate. In a lateral epitaxial growth method, a non-single crystal layer is formed in a portion including the top of the insulating layer, and the non-single crystal layer is first irradiated with an energy beam to make the non-single crystal layer. A method of lateral epitaxial growth, characterized in that the plurality of insulating regions are formed such that each of the plurality of insulating regions has interconnection means to other insulating regions. 2. The lateral epitaxial growth method according to claim 1, wherein the connecting means is made of a material that does not melt or deform at least at the melting point of the semiconductor substrate.
JP58176902A 1983-09-27 1983-09-27 Laterally epitaxial growth Granted JPS6070721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58176902A JPS6070721A (en) 1983-09-27 1983-09-27 Laterally epitaxial growth

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58176902A JPS6070721A (en) 1983-09-27 1983-09-27 Laterally epitaxial growth

Publications (2)

Publication Number Publication Date
JPS6070721A true JPS6070721A (en) 1985-04-22
JPH0377654B2 JPH0377654B2 (en) 1991-12-11

Family

ID=16021749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58176902A Granted JPS6070721A (en) 1983-09-27 1983-09-27 Laterally epitaxial growth

Country Status (1)

Country Link
JP (1) JPS6070721A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0303320A2 (en) * 1987-08-11 1989-02-15 Koninklijke Philips Electronics N.V. A method of forming thin, defect-free, monocrystalline layers of semiconductor materials on insulators

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0303320A2 (en) * 1987-08-11 1989-02-15 Koninklijke Philips Electronics N.V. A method of forming thin, defect-free, monocrystalline layers of semiconductor materials on insulators

Also Published As

Publication number Publication date
JPH0377654B2 (en) 1991-12-11

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