JPH0476490B2 - - Google Patents

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Publication number
JPH0476490B2
JPH0476490B2 JP61048468A JP4846886A JPH0476490B2 JP H0476490 B2 JPH0476490 B2 JP H0476490B2 JP 61048468 A JP61048468 A JP 61048468A JP 4846886 A JP4846886 A JP 4846886A JP H0476490 B2 JPH0476490 B2 JP H0476490B2
Authority
JP
Japan
Prior art keywords
film
forming
layer
semiconductor
laser beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61048468A
Other languages
Japanese (ja)
Other versions
JPS62206816A (en
Inventor
Tadashi Nishimura
Yasuaki Inoe
Kazuyuki Sugahara
Shigeru Kusunoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP61048468A priority Critical patent/JPS62206816A/en
Priority to EP87103147A priority patent/EP0236953B1/en
Priority to DE8787103147T priority patent/DE3780327T2/en
Priority to US07/022,402 priority patent/US4861418A/en
Publication of JPS62206816A publication Critical patent/JPS62206816A/en
Publication of JPH0476490B2 publication Critical patent/JPH0476490B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/903—Dendrite or web or cage technique
    • Y10S117/904—Laser beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は半導体結晶層の製造方法、特に半導
体単結晶の一主面上に厚い絶縁物層を形成した基
体上に多結晶または非晶質の半導体層を形成し、
この半導体層を連続発振のレーザ光で走査しなが
ら溶融させるこそにより下地半導体単結晶を種と
して半導体単結晶層を前記絶縁物層上に製造する
方法に関する。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a method for manufacturing a semiconductor crystal layer, and in particular to a method for manufacturing a semiconductor crystal layer, in particular a polycrystalline or amorphous layer formed on a substrate having a thick insulating layer formed on one principal surface of a semiconductor single crystal. forming a semiconductor layer of
The present invention relates to a method of manufacturing a semiconductor single crystal layer on the insulating layer using a base semiconductor single crystal as a seed by melting the semiconductor layer while scanning it with a continuous wave laser beam.

［従来の技術］ 第３図は従来の、絶縁物層上へ半導体単結晶膜
を製造する方法の概略工程を示す図である。第３
図において、｛100｝面（（001）面またはその等価
な結晶面）を主面とする単結晶シリコン基板（以
下、単にシリコン基板と称する）１１と、シリコ
ン基板１１の一主面上に形成された二酸化シリコ
ン膜からなる比較的厚い酸化膜１２と、酸化膜１
２上に化学的気相成長法（以下、CVD法と称す
る）により形成された多結晶シリコン層１３とか
らなる構造が単結晶膜製造における基体として用
いられる。この多結晶シリコン層１３上にレーザ
光１５を矢印Ｘ方向に照射しながら走査して多結
晶シリコン膜１３を溶融、再結晶化させることに
よりシリコン基板１１の主面の面方位をなぞつて
単結晶化された単結晶シリコン層１４が形成され
る。[Prior Art] FIG. 3 is a diagram schematically showing the steps of a conventional method for manufacturing a semiconductor single crystal film on an insulator layer. Third
In the figure, a single crystal silicon substrate (hereinafter simply referred to as a silicon substrate) 11 having a {100} plane ((001) plane or its equivalent crystal plane) as a principal surface, and a single crystal silicon substrate 11 formed on one principal surface of the silicon substrate 11. A relatively thick oxide film 12 made of silicon dioxide film and an oxide film 1
2 and a polycrystalline silicon layer 13 formed by chemical vapor deposition (hereinafter referred to as CVD) is used as a substrate in the production of a single crystal film. The polycrystalline silicon layer 13 is irradiated and scanned with a laser beam 15 in the direction of the arrow X to melt and recrystallize the polycrystalline silicon film 13, thereby tracing the plane direction of the main surface of the silicon substrate 11 and forming a single crystal. A crystalline single crystal silicon layer 14 is formed.

第４Ａ図ないし第４Ｄ図は従来の単結晶膜製造
工程において基体として用いられる半導体装置の
製造工程を示す断面図である。以下、第４Ａ図な
いし第４Ｄ図を参照して基体として用いられる半
導体装置の製造方法について説明する。 FIGS. 4A to 4D are cross-sectional views showing the manufacturing process of a semiconductor device used as a substrate in a conventional single crystal film manufacturing process. Hereinafter, a method for manufacturing a semiconductor device used as a base will be described with reference to FIGS. 4A to 4D.

第４Ａ図において、まず｛100｝面を主面とす
るシリコン基板１１を950℃の酸化雰囲気にさら
し、その主面上に膜厚500Åの熱酸化膜２１を形
成し、次にCVD法を用いて窒化シリコン膜２２
を膜厚1000Å程度に形成する。 In FIG. 4A, first, a silicon substrate 11 having a {100} plane as its main surface is exposed to an oxidizing atmosphere at 950°C, a thermal oxide film 21 with a thickness of 500 Å is formed on the main surface, and then a CVD method is used to form a thermal oxide film 21 with a thickness of 500 Å. silicon nitride film 22
is formed to a film thickness of approximately 1000 Å.

第４Ｂ図において、写真製版およびエツチング
法を用いて窒化シリコン膜２２を、シリコン基板
１１上の開口部にあたる部分のみ残して他の部分
の窒化シリコン膜を除去する。 In FIG. 4B, photolithography and etching are used to remove the silicon nitride film 22, leaving only the portion corresponding to the opening on the silicon substrate 11, and removing the other portions of the silicon nitride film.

第４Ｃ図において、パターニングされた窒化シ
リコン膜２２をマスクとして、露出した酸化膜２
１を除去し、さらにシリコン基板１１の表面を
5000Å程度エツチングして取去る。次にこのシリ
コン基板１１を950℃の酸化雰囲気中に長時間さ
らすことにより膜厚1μｍ程度の二酸化シリコン
からなる酸化膜１２が所定領域に成長する。 In FIG. 4C, the exposed oxide film 2 is removed using the patterned silicon nitride film 22 as a mask.
1 and then the surface of the silicon substrate 11.
Etch about 5000Å and remove. Next, by exposing this silicon substrate 11 to an oxidizing atmosphere at 950° C. for a long time, an oxide film 12 made of silicon dioxide with a thickness of about 1 μm grows in a predetermined region.

第４Ｄ図において、シリコン基板１１の表面に
残つている窒化シリコン膜２２およびその下部の
酸化膜２１を除去し、CVD法を用いて多結晶シ
リコン層１３を7000Å程度の膜厚に成長させる。
これにより、｛100｝面を主面とするシリコン基板
１１とシリコン基板１１上に形成され、少なくと
もその一部分に下地シリコン基板に達する開口部
２３を有する厚い酸化膜１２と、開口部２３およ
び酸化膜１２上に形成された多結晶シリコン層１
３とからなる基体が形成される。 In FIG. 4D, the silicon nitride film 22 remaining on the surface of the silicon substrate 11 and the oxide film 21 below it are removed, and a polycrystalline silicon layer 13 is grown to a thickness of about 7000 Å using the CVD method.
As a result, the silicon substrate 11 having the {100} plane as its main surface, the thick oxide film 12 formed on the silicon substrate 11 and having an opening 23 reaching the base silicon substrate in at least a portion thereof, and the opening 23 and the oxide film. Polycrystalline silicon layer 1 formed on 12
A base body consisting of 3 is formed.

次に第３図を参照して、第４Ａ図ないし第４Ｄ
図に示される工程によつて形成された基体を用い
て酸化膜（絶縁膜）上に単結晶シリコン層を形成
する方法について説明する。 Next, referring to FIG. 3, FIGS. 4A to 4D
A method of forming a single-crystal silicon layer on an oxide film (insulating film) using a substrate formed by the steps shown in the figure will be described.

第３図に示されるように、開口部２３上の多結
晶シリコン層１３をレーザ光１５の照射によつて
溶融させ、さらにその溶融を開口部２３下のシリ
コン基板１１の表面まで及ばせることにより、固
化、再結晶の際に下地シリコン基板単結晶を種と
したエピタキシヤル成長が生じ、多結晶シリコン
層１３が単結晶化する。したがつて、多結晶シリ
コン層１３に対してレーザ光１５を第３図の矢印
Ｘ方向に走査しながらこれを溶融させることによ
り、横方向、すなわちレーザ光１５走査方向にエ
ピタキシヤル成長が連続して生じ、絶縁物層とし
ての酸化膜１２上にまで単結晶層１４を成長させ
ることができる。 As shown in FIG. 3, by melting the polycrystalline silicon layer 13 above the opening 23 by irradiating the laser beam 15 and further extending the melting to the surface of the silicon substrate 11 below the opening 23, During solidification and recrystallization, epitaxial growth occurs using the underlying silicon substrate single crystal as a seed, and the polycrystalline silicon layer 13 becomes single crystal. Therefore, by melting the polycrystalline silicon layer 13 while scanning it with the laser beam 15 in the direction of arrow X in FIG. 3, epitaxial growth continues in the lateral direction, that is, in the scanning direction of the laser beam 15. The single crystal layer 14 can be grown even on the oxide film 12 as an insulating layer.

［発明が解決しようとする問題点］ 第５Ａ図および第５Ｂ図は多結晶シリコン層を
溶融させるために用いられるレーザ光のパワー分
布および多結晶シリコン溶融時の固液界面および
結晶成長方向を示す図であり、第５Ａ図はレーザ
光のパワー分布を示し、第５Ｂ図は多結晶シリコ
ン層の結晶成長方向を示す図である。[Problems to be Solved by the Invention] Figures 5A and 5B show the power distribution of the laser beam used to melt the polycrystalline silicon layer, the solid-liquid interface during polycrystalline silicon melting, and the crystal growth direction. FIG. 5A is a diagram showing the power distribution of laser light, and FIG. 5B is a diagram showing the crystal growth direction of the polycrystalline silicon layer.

多結晶シリコン層１３を溶融させるために用い
られるレーザ光１５のパワー分布は第５Ａ図に示
されるように、ビーム中心部で高く周辺部で低い
いわゆるガウス型分布をしているため、多結晶シ
リコンが溶融して次に再結晶化する場合、低温の
溶融部周辺から固化が始まり、高温を溶融部中心
部へ向かつて結晶成長していくため、第５Ｂ図に
示されるように、周辺部の雑多な結晶核からの結
晶成長が固液界面３２へ向かつて生じる。この結
果、その結晶成長方向３３が一定せず、シリコン
基板１１の主面の面方位を拾つたエピタキシヤル
結晶成長が阻害されるため、上述の従来の方法で
は、単結晶成長層が得られる領域は開口部２３端
部から50ないし100μｍに限定されていた。 As shown in FIG. 5A, the power distribution of the laser beam 15 used to melt the polycrystalline silicon layer 13 has a so-called Gaussian distribution, which is high at the center of the beam and low at the periphery. When it melts and then recrystallizes, solidification starts from around the low-temperature molten zone, and as the high temperature is directed toward the center of the molten zone, crystal growth occurs, as shown in Figure 5B. Crystal growth from miscellaneous crystal nuclei occurs toward the solid-liquid interface 32. As a result, the crystal growth direction 33 is not constant, and epitaxial crystal growth based on the plane orientation of the main surface of the silicon substrate 11 is inhibited. was limited to 50 to 100 μm from the end of the opening 23.

この上述の問題点を解消するため、ストライプ
状の反射防止膜を多結晶シリコン層１３の上部に
形成し、多結晶シリコン層１３内にレーザ光照射
時に周期的な横方向（レーザ光走査方向に対し）
温度分布を生じせしめてエピタキシヤル結晶成長
の距離を延ばす工夫がなされている。 In order to solve the above-mentioned problem, a striped anti-reflection film is formed on the top of the polycrystalline silicon layer 13, so that the polycrystalline silicon layer 13 is coated periodically in the horizontal direction (in the laser beam scanning direction) during laser beam irradiation. vs.)
Efforts have been made to increase the distance for epitaxial crystal growth by creating a temperature distribution.

第６Ａ図ないし第６Ｃ図は多結晶シリコン層上
にストライプ状に反射防止膜を形成しエピタキシ
ヤル結晶成長距離を増大させる方法を説明するた
めの図であり、たとえば特開昭59−108313号公報
に開示されている。第６Ａ図は基体として用いら
れる半導体装置の平面配置を示し、第６Ｂ図は第
６Ａ図の線−線に沿つた断面構造およびレー
ザ光走査方向を示し、第６Ｃ図は第６Ａ図の−
線に沿つた断面構造を示す図である。第６Ａ図
において、その長さ方向が＜110＞方向またはそ
の等価を方向に延びるストライプ状の反射防止膜
４１が多結晶シリコン層上に形成される。この反
射防止膜４１はこの領域においてレーザ光の反射
を防止し、反射防止膜４１が形成されている領域
下部の多結晶シリコン層の温度を反射防止膜４１
が形成されていない領域の多結晶シリコン層の温
度より高くする機能を有する。このような反射防
止膜４１を設けることにより、第７Ａ図に示され
るような周期的な温度分布をレーザ光照射時に多
結晶シリコン層内に形成することができる。ここ
で、第７Ａ図において、横軸は多結晶シリコン膜
内の位置を示し、縦軸はレーザ光照射時の温度を
示す。 FIGS. 6A to 6C are diagrams for explaining a method of increasing the epitaxial crystal growth distance by forming an antireflection film in stripes on a polycrystalline silicon layer, for example, as described in Japanese Patent Application Laid-Open No. 108313/1983. has been disclosed. FIG. 6A shows a planar arrangement of a semiconductor device used as a base, FIG. 6B shows a cross-sectional structure and laser beam scanning direction along the line--line in FIG. 6A, and FIG. 6C shows a - in FIG. 6A.
FIG. 3 is a diagram showing a cross-sectional structure along a line. In FIG. 6A, a striped antireflection film 41 whose length direction extends in the <110> direction or its equivalent direction is formed on the polycrystalline silicon layer. This anti-reflection film 41 prevents reflection of laser light in this region, and the temperature of the polycrystalline silicon layer below the region where the anti-reflection film 41 is formed is controlled by the anti-reflection film 41.
It has the function of making the temperature higher than that of the polycrystalline silicon layer in the region where it is not formed. By providing such an antireflection film 41, a periodic temperature distribution as shown in FIG. 7A can be formed in the polycrystalline silicon layer during laser beam irradiation. Here, in FIG. 7A, the horizontal axis indicates the position within the polycrystalline silicon film, and the vertical axis indicates the temperature at the time of laser beam irradiation.

このようなストライプ状の反射防止膜４１を設
け、反射防止膜４１のストライプの長さ方向に沿
つてレーザ光１５を矢印Ｘ方向に沿つて走査しな
がら照射すると、多結晶シリコン層内に周期的な
横方向（レーザ光を走査方向に対して）の温度分
布が形成されるため、第７Ｂ図に示されるよう
に、その結晶成長方向３３は反射防止膜４１が形
成されていない領域の中心部から反射防止膜４１
が形成されている領域の多結晶シリコン層へ向か
う方向となる。反射防止膜４１は開口部２３上に
まで達しているため、開口部２３下部の下地基板
単結晶を種とするエピタキシヤル成長が絶縁膜１
２上の温度の低い多結晶シリコン層へと開口部２
３から連続して生じる。したがつて、絶縁層１２
上の再結晶化シリコン層の成長は、開口部２３か
らの下地シリコン基板１１の面方位を拾つたエピ
タキシヤル結晶成長のみが生じることになり、そ
の結晶成長方向が一定（一方方向）となり、その
単結晶成長距離を長くすることができる。 When such a striped anti-reflection film 41 is provided and the laser beam 15 is irradiated while scanning along the length direction of the stripes of the anti-reflection film 41 in the direction of the arrow Since a horizontal temperature distribution (with respect to the scanning direction of the laser beam) is formed, the crystal growth direction 33 is directed to the center of the area where the antireflection film 41 is not formed, as shown in FIG. 7B. Anti-reflection film 41
The direction is toward the polycrystalline silicon layer in the region where is formed. Since the anti-reflection film 41 reaches above the opening 23, the epitaxial growth using the base substrate single crystal below the opening 23 as a seed causes the insulating film 1 to grow.
Opening 2 to the lower temperature polycrystalline silicon layer above 2
It occurs consecutively from 3. Therefore, the insulating layer 12
In the growth of the upper recrystallized silicon layer, only epitaxial crystal growth that picks up the surface orientation of the underlying silicon substrate 11 from the opening 23 occurs, and the crystal growth direction is constant (one direction). Single crystal growth distance can be increased.

しかしこの場合においても、レーザ光１５の走
査速度が１ないし５cm／秒の場合には結晶成長距
離を延ばすことができるものの、スループツト
（処理量）を上げるために、レーザ光１５の走査
速度を20ないし30cm／秒に上げると、単結晶成長
距離は開口部２３端部から200μｍ程度に制限さ
れる。 However, even in this case, although the crystal growth distance can be extended when the scanning speed of the laser beam 15 is 1 to 5 cm/sec, in order to increase the throughput (processing amount), the scanning speed of the laser beam 15 is increased to 20 cm/sec. If the speed is increased to 30 cm/sec, the single crystal growth distance is limited to about 200 μm from the end of the opening 23.

この原因は従来のシリコン単結晶基板に用いら
れるシリコンウエハにおいては、位置検出用のオ
リエンテーシヨンフラツト面が（110）面に設定
されているため、ウエハ上に形成されるあらゆる
パターン（チツプの配列方向、チツプ上に形成さ
れる回路素子のパターン等）がこのオリエンテー
シヨンフラツト面とシリコンウエハとの交線方向
＜110＞方向またはその等価な方向に平行または
垂直方向に設定されるため、反射防止膜４１のス
トライプの長さ方向も＜110＞方向またはその等
価な方向に平行に設定される。したがつて、＜110
＞方向またはこれと等価な方向にレーザ光１５を
走査した場合の結晶成長方向はレーザ光１５の走
査方向が＜110＞方向であつても反射防止膜によ
る温度分布制御により＜100＞方向に近い方向と
なる。この方向は結晶成長によつて特に安定な＜
111＞方向からのずれが大きく、早い走査速度で
レーザ光を走査し、多結晶シリコン層の再結晶化
を行なつた場合、単結晶成長速度がレーザ光の走
査速度に追随することができず、積層欠陥などの
結晶欠陥が発生し、その後結晶粒界が発生するの
である。 The reason for this is that in silicon wafers used for conventional silicon single crystal substrates, the orientation flat plane for position detection is set to the (110) plane. (array direction, pattern of circuit elements formed on the chip, etc.) is set parallel to or perpendicular to the <110> direction of the intersection between the orientation flat surface and the silicon wafer, or its equivalent direction. The length direction of the stripes of the antireflection film 41 is also set parallel to the <110> direction or its equivalent direction. Therefore, <110
Even if the scanning direction of the laser beam 15 is the <110> direction, the crystal growth direction when the laser beam 15 is scanned in the > direction or an equivalent direction is close to the <100> direction due to temperature distribution control by the antireflection film. direction. This direction is particularly stable due to crystal growth.
111> If the deviation from the direction is large and the laser beam is scanned at a fast scanning speed to recrystallize the polycrystalline silicon layer, the single crystal growth rate will not be able to follow the scanning speed of the laser beam. , crystal defects such as stacking faults occur, and then grain boundaries occur.

それゆえ、この発明の目的は上述のような問題
点を解消し、速いレーザ光の走査速度でも結晶欠
陥を発生させることなく単結晶成長させることが
でき、高品質かつ大面積の単結晶半導体層を得る
ことのできる半導体結晶層の製造方法を提供する
ことである。 Therefore, the purpose of the present invention is to solve the above-mentioned problems, to grow a single crystal without generating crystal defects even at a high scanning speed of a laser beam, and to produce a high-quality, large-area single-crystal semiconductor layer. An object of the present invention is to provide a method for manufacturing a semiconductor crystal layer that can obtain the following.

［問題点を解決するための手段］ この発明による半導体結晶層の製造方法は、 （001）面またはその等価な結晶面を主面とす
る半導体単結晶ウエハに形成されてウエハ上の素
子の配列方向を規定するオリエンテーシヨンフラ
ツト面と基板主面との交線の方向を＜110＞方向
と30°以上45°以下の範囲内の角度の方向に設定
し、このオリエンテーシヨンフラツト面と主面と
の交線に対して平行または垂直な方向にストライ
プ状の反射膜または反射防止膜を多結晶または非
晶質シリコン上に周期的に形成し、さらにオリエ
ンテーシヨンフラツト面と30°以上45°以下の角度
をなす１つの＜110＞方向と±10°の範囲の角度を
なす方向にアルゴンレーザ光を走査しながら照射
するようにしたものである。[Means for Solving the Problems] A method for manufacturing a semiconductor crystal layer according to the present invention includes forming a semiconductor crystal layer on a semiconductor single crystal wafer having a (001) plane or an equivalent crystal plane as a main surface, and arranging elements on the wafer. The direction of the intersection line between the orientation flat surface that defines the direction and the main surface of the substrate is set to the <110> direction and an angle within the range of 30° to 45°, and this orientation flat surface A striped reflective film or anti-reflective film is periodically formed on polycrystalline or amorphous silicon in a direction parallel or perpendicular to the intersection line between the main surface and the orientation flat surface. The argon laser beam is scanned and irradiated in a direction forming an angle in the range of ±10° with one <110> direction forming an angle of 45° or more.

［作用］ 反射膜または反射防止膜が有するストライプの
長さ方向に沿つて結晶が成長するため素子の配列
方向と結晶成長方向を一致させることができ、か
つ、この反射防止膜また反射膜により形成される
多結晶シリコン内の温度分布により単結晶エピタ
キシヤル成長方向を最も安定に結晶成長が生じる
結晶方位に向わせることができ、かつストライプ
の長さ方向と異なる方向にアルゴンレーザ光が走
査されるため、速い走査速度のアルゴンレーザ光
を用いても所望の成長方向への走査速度成分は等
価的に遅くなり、かつさらに１回のレーザ光走査
により結晶が成長する領域は細かく区切られた小
領域内となるため、多結晶シリコン膜が溶融、再
結晶化する際に多結晶シリコン膜と下地絶縁層と
熱膨張率の差によりその界面に発生する歪による
結晶欠陥を抑制することができる。[Function] Crystals grow along the length of the stripes of the reflective film or anti-reflective film, so the element arrangement direction and the crystal growth direction can be matched, and the anti-reflective film or reflective film forms The single crystal epitaxial growth direction can be directed to the crystal orientation in which the most stable crystal growth occurs due to the temperature distribution within the polycrystalline silicon, and the argon laser beam is scanned in a direction different from the length direction of the stripe. Therefore, even if an argon laser beam with a fast scanning speed is used, the scanning speed component in the desired growth direction will be equivalently slow, and furthermore, the area where the crystal will grow with one laser beam scan will be divided into finely divided small areas. Since the polycrystalline silicon film is within the region, it is possible to suppress crystal defects due to strain generated at the interface between the polycrystalline silicon film and the underlying insulating layer due to the difference in coefficient of thermal expansion when the polycrystalline silicon film is melted and recrystallized.

［発明の実施例］ 以下にこの発明の実施例について図面を参照し
て説明する。[Embodiments of the Invention] Examples of the invention will be described below with reference to the drawings.

第１Ａ図ないし第１Ｄ図はこの発明の一実施例
において基体として用いられる半導体装置の概略
構成を示す図であり、第１Ａ図はこの発明におい
て用いられる半導体ウエハの一例を構成を示す平
面図であり、第１Ｂ図は第１Ａ図に示されるウエ
ハに形成されるチツプ領域の拡大平面図であり、
第１Ｃ図は第１Ｂ図の−線に沿つた断面構造
を示す図であり、第１Ｄ図は第１Ｂ図の−線
に沿つた断面構造を示す図である。以下、第１Ａ
図ないし第１Ｄ図を参照してこの発明の一実施例
において基体として用いられる半導体装置の構成
について説明する。 1A to 1D are diagrams showing a schematic configuration of a semiconductor device used as a base in an embodiment of the present invention, and FIG. 1A is a plan view showing the configuration of an example of a semiconductor wafer used in the present invention. 1B is an enlarged plan view of a chip region formed on the wafer shown in FIG. 1A;
1C is a diagram showing a cross-sectional structure taken along the - line in FIG. 1B, and FIG. 1D is a diagram showing a cross-sectional structure taken along the - line in FIG. 1B. Below, 1A
The structure of a semiconductor device used as a base in an embodiment of the present invention will be described with reference to the drawings to FIG. 1D.

第１Ａ図において、この発明の一実施例である
結晶膜製造方法において基体として用いられる半
導体ウエハ５０は、その主面を（001）面または
その等価な結晶面（以下、単に（001）面と称す）
とし、かつ方位検出用のオリエンテーシヨンフラ
ツト面６０が（510）面に設定される。このシリ
コン半導体ウエハ５０上にチツプ５１が、その短
辺または長辺がオリエンテーシヨンフラツト面６
０と平行となるように配列される。次に第１Ｂ図
ないし第１Ｄ図を参照して個々の半導体チツプの
構成について説明する。 In FIG. 1A, a semiconductor wafer 50 used as a base in the crystal film manufacturing method which is an embodiment of the present invention has its main surface as the (001) plane or its equivalent crystal plane (hereinafter simply referred to as the (001) plane). )
In addition, the orientation flat plane 60 for direction detection is set to the (510) plane. A chip 51 is placed on this silicon semiconductor wafer 50, with its short side or long side facing the orientation flat surface 6.
Arranged parallel to 0. Next, the structure of each semiconductor chip will be explained with reference to FIGS. 1B to 1D.

チツプ領域５１は、開口部５７によりその領域
が規定される（001）面を主面とするシリコン単
結晶基板５２と、シリコン単結晶基板５２上に開
口部５７を有して形成される二酸化シリコンであ
る絶縁層５３と、絶縁層５３および開口部５７上
に形成される溶融させるべき多結晶シリコン層５
４と、多結晶シリコン層５４上に形成され、アル
ゴンレーザ光に対し反射防止膜となる膜厚2500A
の二酸化シリコン層を５５と、二酸化シリコン層
５５上にその長さ方向が＜510＞方向に設定され
るストライプ状のシリコン窒化膜５６とから構成
される。ストライプ状のシリモン窒化膜５６のス
トライプの長さ方向はオリエンテーシヨンフラツ
ト面６０と垂直または平行な方向すなわち＜510
＞方向に設定され、かつその膜圧は550Åであり、
幅10μｍ、間隔5μｍに設定され、反射防止膜とな
る二酸化シリコン層５５のレーザ光に対する反射
率を周期的に変化させ、多結晶シリコン層５４内
にレーザ光照射時に所望の温度分布を与える。反
射防止膜となる二酸化シリコン層５０の条件は波
長λ＝5145Åの連続発振アルゴンレーザ光に対し
て設定され、アルゴンレーザ光をほぼ100％透過
させる。したがつて上述の構成においては、スト
ライプ状のシリコン窒化膜５６が形成されている
領域の下の多結晶シリコン層は、シリコン窒化膜
５６が形成されていない領域の下部の多結晶シリ
コン層の温度よりも低くなり、第７Ａ図に示され
る温度分布をレーザ光照射事に多結晶シリコン層
５４内に形成する。チツプの配列方向はオリエン
テーシヨンフラツト面６０に規定される。 The chip region 51 includes a silicon single crystal substrate 52 whose main surface is a (001) plane defined by an opening 57, and a silicon dioxide substrate formed on the silicon single crystal substrate 52 with an opening 57. an insulating layer 53, and a polycrystalline silicon layer 5 to be melted formed on the insulating layer 53 and the opening 57.
4, a film with a thickness of 2500 A is formed on the polycrystalline silicon layer 54 and serves as an anti-reflection film against argon laser light.
55, and a striped silicon nitride film 56 whose length direction is set in the <510> direction on the silicon dioxide layer 55. The length direction of the stripes of the striped silimon nitride film 56 is perpendicular or parallel to the orientation flat surface 60, that is, <510
> direction, and its film thickness is 550 Å,
The width is set to 10 .mu.m and the interval is 5 .mu.m, and the reflectance of the silicon dioxide layer 55, which serves as an antireflection film, to the laser beam is periodically changed to provide a desired temperature distribution within the polycrystalline silicon layer 54 during irradiation with the laser beam. The conditions for the silicon dioxide layer 50, which serves as an antireflection film, are set for continuous wave argon laser light with a wavelength λ=5145 Å, so that almost 100% of the argon laser light is transmitted. Therefore, in the above structure, the temperature of the polycrystalline silicon layer under the region where the striped silicon nitride film 56 is formed is lower than that of the polycrystalline silicon layer under the region where the silicon nitride film 56 is not formed. The temperature distribution shown in FIG. 7A is formed in the polycrystalline silicon layer 54 by laser beam irradiation. The direction in which the chips are arranged is defined by the orientation flat surface 60.

第２Ａ図ないし第２Ｃ図はこの発明の一実施例
である半導体結晶層の製造工程段階を示す図であ
る。以下、第２Ａ図ないし第２Ｃ図を参照してこ
の発明の一実施例である半導体結晶膜の製造方法
について説明する。 FIGS. 2A to 2C are diagrams showing the manufacturing process steps of a semiconductor crystal layer according to an embodiment of the present invention. Hereinafter, a method for manufacturing a semiconductor crystal film, which is an embodiment of the present invention, will be described with reference to FIGS. 2A to 2C.

まず第２Ａ図において、アルゴンレーザ光は＜
110＞方向に走査される。このとき二酸化シリコ
ン膜５５とシリコン窒化膜５６からなる反射防止
膜によりアルゴンレーザ光に対する反射率が周期
的に変化するため、アルゴンレーザ光照射時のレ
ーザ光を吸収した多結晶シリコン層内の温度分布
は第７Ａ図に示されるごとくシリコン窒化膜５６
が設けられている領域下部の多結晶シリコン層の
温度が低く、シリコン窒化膜５６が設けられてい
ない領域下部の多結晶シリコン層の温度が高くな
る。またこのときの温度分布は第２Ａ図の上部に
も位置合わせして示されている。この結果、上述
の条件で反射防止膜が形成されている場合、レー
ザ光照射領域における固液界面７０はアルゴンレ
ーザ光の走査方向とは異なり、第２Ａ図に示され
るように鋸歯状となるが主たる方向が＜210＞方
向または＜221＞方向となる。このとき溶融領域
は固化の際、開口部５７を通じて下地の単結晶シ
リコン基板を種結晶としてエピタキシヤル成長す
る（矢印７１）。すなわち、アルゴンレーザ光の
ビーム径100μｍ程度の溶融幅でアルゴンレーザ
光が走査速度25cm／秒で走査、照射された際、多
結晶シリコン層が溶融、再結晶化する際、レーザ
光の走査速度、方向とほぼ関係なく＜210＞方向
または＜211＞方向にその結晶面固有の結晶成長
速度で矢印７１方向に単結晶エピタキシヤル成長
する。 First, in Figure 2A, the argon laser beam is <
110> scanned in the direction. At this time, the reflectance of the argon laser beam changes periodically due to the anti-reflection film made of the silicon dioxide film 55 and the silicon nitride film 56, so the temperature distribution within the polycrystalline silicon layer that absorbed the laser beam during irradiation with the argon laser beam is a silicon nitride film 56 as shown in FIG. 7A.
The temperature of the polycrystalline silicon layer below the region where silicon nitride film 56 is provided is low, and the temperature of the polycrystalline silicon layer below the region where silicon nitride film 56 is not provided becomes high. The temperature distribution at this time is also shown in alignment with the upper part of FIG. 2A. As a result, when the antireflection film is formed under the above-mentioned conditions, the solid-liquid interface 70 in the laser beam irradiation area differs from the scanning direction of the argon laser beam and has a sawtooth shape as shown in FIG. 2A. The main direction is the <210> direction or the <221> direction. At this time, during solidification, the molten region grows epitaxially through the opening 57 using the underlying single crystal silicon substrate as a seed crystal (arrow 71). That is, when the polycrystalline silicon layer is melted and recrystallized when the argon laser beam is scanned and irradiated at a scanning speed of 25 cm/sec with a melting width of about 100 μm in beam diameter, the scanning speed of the laser beam, A single crystal epitaxially grows in the direction of arrow 71 at a crystal growth rate specific to the crystal plane in the <210> direction or the <211> direction, almost regardless of the direction.

２回目のレーザ光の走査について第２Ｂ図を参
照して説明する。１回目のアルゴンレーザ光の走
査が済むと、アルゴンレーザ光を走査方向と垂直
な方向に30μｍ程度移動させた後再び＜110＞方
向に照射走査する。２回目のレーザ光による溶融
領域は前回のレーザ光の走査により溶融された領
域にまで達することになり、開口部５７に通じて
いる箇所では開口部５７を通じて下地単結晶基板
を種としたエピタキシヤル成長が矢印７１方向に
生じ、かつ１回目のレーザ光走査により単結晶成
長した領域に隣接する領域ではその単結晶成長領
域を種結晶としたエピタキシヤル成長が生じる。 The second laser beam scan will be explained with reference to FIG. 2B. When the first scan with the argon laser beam is completed, the argon laser beam is moved approximately 30 μm in a direction perpendicular to the scanning direction, and then irradiation and scanning is performed in the <110> direction again. The area melted by the second laser beam will reach the area melted by the previous scan of the laser beam, and in the area leading to the opening 57, the epitaxial layer with the base single crystal substrate as a seed will be formed through the opening 57. Growth occurs in the direction of arrow 71, and epitaxial growth occurs in a region adjacent to the region where the single crystal has grown by the first laser beam scan, using the single crystal growth region as a seed crystal.

第２Ｃ図において３回目のアルゴンレーザ光走
査が行なわれる。この場合も、２回目のレーザ光
走査と同様にして、下地単結晶基板を種としたエ
ピタキシヤル成長および前回のレーザ光走査によ
り単結晶成長した領域を種結晶としたエピタキシ
ヤル成長が生じ単結晶成長領域がさらに長くな
る。以下、このレーザ光走査を繰返すことにより
ウエハ上の多結晶シリコン層を単結晶化させる。
このとき、１回のレーザ光走査により単結晶成長
する距離はレーザ光走査方向と異なるため、せい
ぜい40ないし50μｍ程度である。つまり１回の結
晶成長距離はストライプの長さ方向に沿つて固液
界面と前回の固液界面との間の小領域でその結晶
面固有の結晶速度で生じるため、アルゴンレーザ
光の走査速度は25cm／秒と速いが、単結晶成長そ
のものはごく細かく区切られた領域内（そのとき
の固液界面と前回のレーザ光照射による固液界面
との間の領域）内でその結晶面固有の結晶成長速
度で生じる。したがつて、結果的にレーザ光の走
査速度の結晶成長方向成分は小さくなり、結晶欠
陥（積層欠陥等）のない極めて高品質な単結晶層
を大面積にわたつて得ることができる。また１回
のレーザ光走査による単結晶成長距離は40ないし
50μｍ程度と小さいため、単結晶シリコン層と下
地の絶縁層との熱膨張率の差による歪が発生する
こともないので高品質な単結晶層が得られる。し
かもアルゴンレーザ光の走査速度は25ないし30
cm／秒と比較的速いので、ウエハ全体にわたつて
短時間で単結晶層を形成することができる。 In FIG. 2C, the third argon laser beam scan is performed. In this case as well, in the same manner as the second laser beam scan, epitaxial growth occurs using the underlying single crystal substrate as a seed crystal, and epitaxial growth using the area where the single crystal was grown by the previous laser beam scan as a seed crystal occurs, resulting in a single crystal. The growth area becomes longer. Thereafter, by repeating this laser beam scanning, the polycrystalline silicon layer on the wafer is made into a single crystal.
At this time, the distance over which the single crystal grows by one laser beam scan is different from the laser beam scanning direction, so it is about 40 to 50 μm at most. In other words, the distance of one crystal growth occurs in a small region between the solid-liquid interface and the previous solid-liquid interface along the length direction of the stripe at the crystal speed specific to that crystal plane, so the scanning speed of the argon laser beam is Although it is fast at 25 cm/sec, the single crystal growth itself grows within a very finely divided region (the region between the solid-liquid interface at that time and the solid-liquid interface caused by the previous laser beam irradiation). Occurs at growth rate. Therefore, as a result, the crystal growth direction component of the scanning speed of the laser beam becomes small, and an extremely high quality single crystal layer free of crystal defects (such as stacking faults) can be obtained over a large area. In addition, the single crystal growth distance with one laser beam scan is 40 or more.
Since the thickness is as small as approximately 50 μm, distortion due to the difference in thermal expansion coefficient between the single crystal silicon layer and the underlying insulating layer does not occur, so a high quality single crystal layer can be obtained. Moreover, the scanning speed of the argon laser beam is 25 to 30
Since it is relatively fast at cm/sec, a single crystal layer can be formed over the entire wafer in a short time.

なお、上記実施例においては、反射防止膜とし
て膜厚2500Åの二酸化シリコン膜とストライプ状
に形成された膜厚550Åのシリコン窒化膜で構成
しているが、これに限定されず、膜厚2000〜3000
Åの二酸化シリコン膜上に幅８〜15μｍ、間隔４
〜7μｍでストライプ状に膜厚400〜800Åのシリ
コン窒化膜を形成した構造、膜厚100〜200Åの二
酸化シリコン膜上に幅４〜7μｍ、間隔８〜15μｍ
で膜厚500〜600Åのストライプ状にシリコン窒化
膜を形成し、さらに膜厚60〜150Åのシリコン窒
化膜を形成した構造を用いても同様の効果が得ら
れる。また、反射防止膜の機能を考えれば、レー
ザ波長に対して反射率を周期的に変化させ得る構
造であれば種々の方法が使用可能であることは明
らかである。すなわちたとえばシリコン窒化膜を
１層のみでストライプ状に形成してもよいし、こ
のような屈折率の変化による反射防止膜を形成す
るのではなく、高融点金属またはそのシリサイド
をストライプ状に形成してその領域で直接レーザ
光を反射させるように構成してもよい。また、絶
縁膜上にストライプ状の多結晶シリコン膜を形成
し、この多結晶シリコン膜でレーザ光を吸収する
ことより、このストライプ状の多結晶シリコン膜
が形成された領域下部の温度を下げるように構成
しても同様の効果が得られることは明らかであ
る。 In the above embodiment, the anti-reflection film is composed of a silicon dioxide film with a thickness of 2500 Å and a silicon nitride film with a thickness of 550 Å formed in stripes, but the anti-reflection film is not limited to this. 3000
Width 8-15 μm, spacing 4 on silicon dioxide film of Å
A structure in which a silicon nitride film with a thickness of 400 to 800 Å is formed in stripes of ~7 μm, with a width of 4 to 7 μm and an interval of 8 to 15 μm on a silicon dioxide film with a thickness of 100 to 200 Å.
A similar effect can be obtained by using a structure in which a silicon nitride film is formed in stripes with a thickness of 500 to 600 Å, and a silicon nitride film is further formed with a thickness of 60 to 150 Å. Further, considering the function of the antireflection film, it is clear that various methods can be used as long as the structure allows the reflectance to be periodically changed with respect to the laser wavelength. That is, for example, a single silicon nitride film may be formed in a stripe shape, or instead of forming an antireflection film based on such a change in refractive index, a high melting point metal or its silicide may be formed in a stripe shape. Alternatively, the laser beam may be directly reflected in that area. In addition, by forming a striped polycrystalline silicon film on the insulating film and absorbing laser light, the temperature below the area where the striped polycrystalline silicon film is formed is lowered. It is clear that similar effects can be obtained even if the configuration is configured as follows.

また、反射防止膜のストライプの間隔および膜
厚によつて反射防止効果が変化し、それに応じて
レーザ光照射時に生じる多結晶シリコン層の固液
界面の方向が変化するので、必要とされるパター
ンサイズ等の条件に応じてオリエンテーシヨンフ
ラツト面の方向、すなわち反射防止膜のストライ
プの方向およびレーザ光の走査方向をそれぞれ適
当に調整すればより良い結果が得られることは言
うまでもない。 In addition, the antireflection effect changes depending on the stripe spacing and film thickness of the antireflection film, and the direction of the solid-liquid interface of the polycrystalline silicon layer that occurs during laser beam irradiation changes accordingly. It goes without saying that better results can be obtained by appropriately adjusting the direction of the orientation flat surface, that is, the direction of the stripes of the antireflection film and the scanning direction of the laser beam, depending on conditions such as size.

また、上記実施例においては開口部５７をチツ
プ領域を規定するように設けてどの領域からでも
単結晶成長ができるようにしているが、その開口
部５７の設けられる方向および形状は図に示され
るものに限定されるものではない。また開口部５
７がチツプ領域を取囲む必要もない。 Further, in the above embodiment, the opening 57 is provided to define the chip region so that single crystal growth can be performed from any region, but the direction and shape of the opening 57 are shown in the figure. It is not limited to things. Also, the opening 5
7 does not need to surround the chip area.

または溶融されるべき半導体層として多結晶シ
リコン層を用いているが非晶質シリコンを用いて
も同様の効果を得ることができる。 Alternatively, although a polycrystalline silicon layer is used as the semiconductor layer to be melted, the same effect can be obtained by using amorphous silicon.

［発明の効果］ 以上のようにこの発明によれば、（001）面また
はその等価な結晶面を主面とする単結晶半導体ウ
エハ側面に主面との交線が＜110＞方向またはそ
の等価な方向と30°から45°間の角度をなすような
オリエンテーシヨンフラツト面を形成し、溶融さ
るべき非晶質または多結晶の半導体層上に形成さ
れるストライプ状の反射膜または反射防止膜のス
トライプの長さ方向をオリエンテーシヨンフラツ
ト面と単結晶半導体ウエハ主面との交線と平行ま
たは垂直な方向に形成し、かつ多結晶または非晶
質半導体を溶融させるためのアルゴンレーザ光の
走査方向を＜110＞方向またはその等価な方向と
±10°の範囲の角度をなす方向に設定しているの
で、容易に反射防止膜または反射膜の長さ方向を
設定することができ、かつ単結晶エピタキシヤル
成長方向をその結晶面固有の成長速度の大きい方
向へ向かわせることができるとともに素子配列方
向に向かわせることができ、かつ、１回のアルゴ
ンレーザ光走査による単結晶成長距離は小さくな
るので、結晶欠陥が発生することなく短時間で大
面積かつ高品質の単結晶半導体層を得ることがで
きる。[Effects of the Invention] As described above, according to the present invention, the side surface of a single crystal semiconductor wafer whose main surface is the (001) plane or its equivalent crystal plane has a line of intersection with the main surface in the <110> direction or its equivalent crystal plane. A striped reflective film or antireflection film formed on an amorphous or polycrystalline semiconductor layer to be melted, forming an orientation flat surface that forms an angle between 30° and 45° with the direction of the film. An argon laser for forming film stripes in a direction parallel or perpendicular to the line of intersection between the orientation flat surface and the main surface of a single crystal semiconductor wafer, and for melting polycrystalline or amorphous semiconductors. Since the scanning direction of the light is set at an angle within ±10° with the <110> direction or its equivalent direction, the length direction of the anti-reflection film or reflective film can be easily set. , and the single crystal epitaxial growth direction can be directed to the direction where the growth rate specific to the crystal plane is high, and the single crystal epitaxial growth direction can be directed to the element arrangement direction, and the single crystal growth distance by one argon laser beam scan can be is small, so a large-area, high-quality single-crystal semiconductor layer can be obtained in a short time without crystal defects occurring.

【図面の簡単な説明】[Brief explanation of the drawing]

第１Ａ図はこの発明の一実施例である半導体結
晶層の製造方法において用いられる半導体ウエハ
の平面図を示す図である。第１Ｂ図は第１Ａ図に
示されるチツプ領域の拡大平面図である。第１Ｃ
図は第１Ｂ図の−線に沿つた断面構造を示す
図である。第１Ｄ図は第１Ｂ図の−線に沿つ
た断面構造を示す図である。第２Ａ図ないし第２
Ｃ図はこの発明の一実施例である半導体結晶層の
製造方法の工程を示す図である。第３図は従来の
半導体単結晶層の製造方法を示す概略面断面図で
ある。第４Ａ図ないし第４Ｄ図は従来の単結晶製
造方法において基体として用いられる半導体装置
の製造工程を示す断面図である。第５Ａ図は多結
晶または非晶質半導体層を溶融するために用いら
れるレーザ光のパワー分布を示す図である。第５
Ｂ図は第５Ａ図に示されるレーザ光を用いた際の
多結晶または非晶質半導体層に発生する固液界面
および結晶成長方向を示す図である。第６Ａ図は
従来の改良された半導体単結晶層の製造方法にお
いて基体として用いられる半導体装置の平面配置
を示す図である。第６Ｂ図は第６Ａ図の−線
に沿つた断面構造およびレーザ光走査方向を示す
図であり従来の改良された半導体単結晶層製造方
法工程を概略的に示す図である。第６Ｃ図は第６
Ａ図の−線に沿つた断面構造を示す図であ
る。第７Ａ図は第６Ａ図ないし第６Ｃ図において
示される反射防止膜の効果により発生される多結
晶または非晶質半導体層におけるエネルギー線照
射時の温度分布を示す図である。第７Ｂ図は第７
Ａ図に示される温度分布が生じた際の結晶成長方
向およびレーザ走査方向を示す図である。 図において、５０は（001）面またはその等価
な結晶面を主面としてオリエンテーシヨンフラツ
ト面として（510）面を有する半導体ウエハ、５
２は単結晶シリコン基板、５３は厚い酸化膜、５
４は溶融されるべき多結晶または非晶質半導体
層、５５は反射防止膜となる二酸化シリコン層、
５６はストライプ状に形成されたシリコン窒化
膜、５７は開口部、６０はオリエンテーシヨンフ
ラツト面である。なお、図中、同一符号は同一ま
たは相当部分を示す。 FIG. 1A is a plan view of a semiconductor wafer used in a method for manufacturing a semiconductor crystal layer according to an embodiment of the present invention. FIG. 1B is an enlarged plan view of the chip area shown in FIG. 1A. 1st C
The figure is a diagram showing a cross-sectional structure taken along the - line in FIG. 1B. FIG. 1D is a diagram showing a cross-sectional structure taken along the - line in FIG. 1B. Figure 2A or Figure 2
FIG. C is a diagram showing steps of a method for manufacturing a semiconductor crystal layer according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing a conventional method for manufacturing a semiconductor single crystal layer. FIGS. 4A to 4D are cross-sectional views showing the manufacturing process of a semiconductor device used as a substrate in a conventional single crystal manufacturing method. FIG. 5A is a diagram showing the power distribution of laser light used to melt a polycrystalline or amorphous semiconductor layer. Fifth
Figure B is a diagram showing the solid-liquid interface and crystal growth direction generated in a polycrystalline or amorphous semiconductor layer when the laser beam shown in Figure 5A is used. FIG. 6A is a diagram showing a planar arrangement of a semiconductor device used as a substrate in a conventional improved method for manufacturing a semiconductor single crystal layer. FIG. 6B is a diagram showing a cross-sectional structure and a laser beam scanning direction taken along the line - in FIG. 6A, and is a diagram schematically showing steps of a conventional improved semiconductor single crystal layer manufacturing method. Figure 6C is the 6th
It is a figure which shows the cross-sectional structure along the - line of A figure. FIG. 7A is a diagram showing the temperature distribution during energy ray irradiation in a polycrystalline or amorphous semiconductor layer generated by the effect of the antireflection film shown in FIGS. 6A to 6C. Figure 7B is the 7th
It is a figure which shows the crystal growth direction and laser scanning direction when the temperature distribution shown in figure A occurs. In the figure, 50 is a semiconductor wafer having a (001) plane or its equivalent crystal plane as a main plane and a (510) plane as an orientation flat plane;
2 is a single crystal silicon substrate, 53 is a thick oxide film, 5
4 is a polycrystalline or amorphous semiconductor layer to be melted; 55 is a silicon dioxide layer serving as an antireflection film;
56 is a silicon nitride film formed in a stripe shape, 57 is an opening, and 60 is an orientation flat surface. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 １ 実質的に（001）面をなす結晶面を主面とす
るダイヤモンド型構造を有する半導体単結晶ウエ
ハの側面に、前記主面となす交線が前記主面上の
＜110＞方向と30°以上45°以下の範囲内にある角
度をなすようにオリエンテーシヨンフラツト面を
形成するステツプと、 前記主面上に、少なくともその一部分に前記主
面上に達する開口部を有する第１の絶縁物層を形
成するステツプと、 前記開口部上および前記第１の絶縁物層上に非
単結晶の第１の半導体層を形成するステツプと、 前記第１の半導体層上に少なくとも１層からな
り、その長さ方向が前記オリエンテーシヨンフラ
ツト面と前記主面との交線と実質的に平行または
垂直にされ、かつその幅および間隔が予め定めら
れたストライプが周期的に形成されるストライプ
状の膜厚分布を有し、照射レーザ光に対し周期的
な反射率変化を与える反射率変化層を形成するス
テツプと、 前記反射率変化層を介して前記レーザ光を、前
記オリエンテーシヨンフラツト面の前記交線と
30°以上45°以下の範囲の角度の方向をなす＜110
＞方向を基準として−10°以上＋10°以下の範囲内
の角度の方向に走査し照射するステツプとを含
む、半導体結晶層の製造方法。 ２ 前記反射率変化層を形成するステツプは、 前記第１の半導体層上に膜厚2000ないし3000Å
の二酸化シリコン膜を形成するステツプと、 前記二酸化シリコン膜上に膜厚400ないし800Å
の窒化シリコン膜を幅８ないし15μｍ、間隔４な
いし7μｍで前記ストライプ状に形成するステツ
プとを備える、特許請求の範囲第１項記載の半導
体結晶層の製造方法。 ３ 前記反射率変化層を形成するステツプは、 前記第１半導体層上に膜厚100ないし200Åの二
酸化シリコン膜を形成するステツプと、 前記二酸化シリコン膜上に膜厚500ないし600Å
のシリコン窒化膜を幅４ないし7μｍ、間隔８な
いし15μｍの前記ストライプ状に形成するステツ
プと、 前記シリコン窒化膜上および前記二酸化シリコ
ン膜上に膜厚60ないし150Åのシリコン窒化膜を
形成するステツプとを備える、特許請求の範囲第
１項記載の半導体結晶層の製造方法。 ４ 前記半導体単結晶ウエハはシリコンからな
る、特許請求の範囲第１項記載の半導体結晶の製
造方法。 ５ 前記第１の半導体層はシリコンで構成され
る、特許請求の範囲第１項記載の半導体結晶層の
製造方法。[Scope of Claims] 1. A side surface of a semiconductor single crystal wafer having a diamond-shaped structure whose main surface is a substantially (001) crystal plane, such that an intersection line with the main surface is << a step for forming an orientation flat surface to form an angle within a range of 30° or more and 45° or less with the 110>direction; and an opening on the main surface that reaches at least a portion of the main surface. forming a first non-single crystal semiconductor layer on the opening and on the first insulating layer; and forming a first non-single crystal semiconductor layer on the first semiconductor layer. the length direction of which is substantially parallel or perpendicular to the line of intersection between the orientation flat surface and the principal surface, and whose width and spacing are predetermined, the stripes are arranged periodically. forming a reflectance change layer having a stripe-like film thickness distribution and giving periodic reflectance changes to the irradiated laser beam; and directing the laser beam through the reflectance change layer. , and the intersection line of the orientation flat surface.
Forms the direction of an angle in the range of 30° or more and 45° or less <110
> scanning and irradiating in the direction of an angle within the range of -10° or more and +10° or less with reference to the direction. 2. The step of forming the reflectance change layer includes forming a film thickness of 2000 to 3000 Å on the first semiconductor layer.
forming a silicon dioxide film with a thickness of 400 to 800 Å on the silicon dioxide film;
2. The method of manufacturing a semiconductor crystal layer according to claim 1, further comprising the step of forming a silicon nitride film having a width of 8 to 15 μm and an interval of 4 to 7 μm in the form of stripes. 3. The step of forming the reflectance change layer includes forming a silicon dioxide film with a thickness of 100 to 200 Å on the first semiconductor layer, and a step of forming a silicon dioxide film with a thickness of 500 to 600 Å on the silicon dioxide film.
forming a silicon nitride film with a width of 4 to 7 μm and an interval of 8 to 15 μm in the form of stripes; and forming a silicon nitride film with a thickness of 60 to 150 Å on the silicon nitride film and the silicon dioxide film. A method for manufacturing a semiconductor crystal layer according to claim 1, comprising: 4. The method for manufacturing a semiconductor crystal according to claim 1, wherein the semiconductor single crystal wafer is made of silicon. 5. The method of manufacturing a semiconductor crystal layer according to claim 1, wherein the first semiconductor layer is made of silicon.
JP61048468A 1986-03-07 1986-03-07 Manufacture of semiconductor crystal layer Granted JPS62206816A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP61048468A JPS62206816A (en) 1986-03-07 1986-03-07 Manufacture of semiconductor crystal layer
EP87103147A EP0236953B1 (en) 1986-03-07 1987-03-05 Method of manufacturing semiconductor crystalline layer
DE8787103147T DE3780327T2 (en) 1986-03-07 1987-03-05 METHOD FOR PRODUCING A SEMICONDUCTOR CRYSTAL LAYER.
US07/022,402 US4861418A (en) 1986-03-07 1987-03-06 Method of manufacturing semiconductor crystalline layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61048468A JPS62206816A (en) 1986-03-07 1986-03-07 Manufacture of semiconductor crystal layer

Publications (2)

Publication Number Publication Date
JPS62206816A JPS62206816A (en) 1987-09-11
JPH0476490B2 true JPH0476490B2 (en) 1992-12-03

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Country Link
US (1) US4861418A (en)
EP (1) EP0236953B1 (en)
JP (1) JPS62206816A (en)
DE (1) DE3780327T2 (en)

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DE3780327D1 (en) 1992-08-20
EP0236953B1 (en) 1992-07-15
JPS62206816A (en) 1987-09-11
EP0236953A3 (en) 1989-07-26
EP0236953A2 (en) 1987-09-16
DE3780327T2 (en) 1993-03-11
US4861418A (en) 1989-08-29

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