JPS6068716A - Signal discriminating circuit - Google Patents

Abstract

PURPOSE:To obtain a signal discriminating circuit capable of discriminating even two signals having a level difference by using two circuits generating a trigger signal in response to the period of two signals and two pulse generating circuits or the like generating a pulse of a prescribed time width. CONSTITUTION:A trigger signal is generated at the same time from circuits 1, 2 generating a signal in synchronizing with an input signal and consisting of a differentiation circuit when any of signals S1 and S2 having respectively frequencies f1 and f2 is inputted, and the trigger signal is inputted to pulse generating circuits 3, 4. The pulse generating circuits 3, 4 outputs pulse signals S3, S4 having time widths of t1, t2 having the relation of 1/f1<t1<1/f2 and 1/f1<t2<2/f2, the state of the signal S3 is read by a D-FF6 with a clock S5 generated in synchronizing with the rear edge of the signal S4 from a clock generating circuit 5, and when the signal S1 having the frequency f1 is inputted, an output of the FF6 goes to L and when the signal S2 having the frequency f2 is inputted, the output of the FF6 goes to H.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a signal discrimination circuit that discriminates between a first signal having a frequency fl and a second signal having a frequency 12 (where fl < f2).

, (Prior Art) Conventional signal discriminating circuits have a method of converting each signal into a direct current or pulsating current with a large amplitude depending on the respective frequency, and detecting the level of the converted output to distinguish between the two signals. There is a method designed to determine the However, in such an analog discrimination method, when the height of the conversion output is adjusted to discriminate between signals with a large frequency difference, the height of the conversion output is adjusted to discriminate between signals with a small frequency difference. It may become impossible to obtain various level differences, and in such a case, it is necessary to adjust the conversion output or its detection sensitivity. Therefore, it has been desired to be able to easily discriminate signals without the need for the above-mentioned adjustment.

(Objective) An object of the present invention is to enable signals to be easily discriminated without requiring such adjustment.

(Example) Hereinafter, the present invention will be described in detail based on an example shown in the drawings. FIG. 1 is a circuit diagram of this embodiment. This embodiment will be explained by applying it to a circuit that discriminates between a first signal S1 having a frequency rl and a second signal S2 having a frequency f2 (fl<f2). This discrimination circuit uses both the signals Sl and S2.
Based on the period of each signal $1, S2 (1/fl, 1/
It has a trigger signal generation circuit 1.2 that generates trigger signals Sl' and S2' corresponding to [2]. The eleventh signal generation circuit 1 includes diodes DI and D2, resistors R1 and R2,
Similarly, the second tri-signal generating circuit 2 includes a capacitor C1, and a diode 3. D4, resistors R3 and R4, and capacitor C2. Trigger signal S1. S2 is the first
．． The signal is applied to the second pulse generating circuits 3 and 4.

The first pulse generating circuit 3 includes an inverter circuit G1. as a monostable multivibrator. G2, a diode D5, a resistor R5, and a capacitor C3, and the second pulse generating circuit 4 is also an inverter circuit G3.G2 as a monostable multivibrator. G4, Guio)? D6, resistor R6, and capacitor C4. The first pulse generating circuit 3 generates a first output pulse S3 having a pulse width ti (where 1/f2<tl<1/[1) by being supplied with a trigger signal Sl' (vJl). This output pulse width t1 is the capacitor C
3 and resistor R5 by appropriately setting the time constant. Further, the second pulse generation circuit 4
When the bird is given the signal S2', the pulse width becomes t.
2 (where 1/fl<t2<2/12)
Generates an output pulse S4.

This output pulse width t2 can also be changed by setting the time constants of the capacitor C4 and the resistor R6.

The second output pulse S4 is given to the clock pulse generation circuit 5. Clock pulse generation circuit 5 includes an inverter circuit G5, a capacitor C5, a resistor R7, and a diode D7. This clock pulse generation circuit generates a second output pulse S4.
is inverted by an inverter circuit G5 and differentiated by a capacitor C5 and a resistor R7, and a positive differential pulse is outputted by a diode D7 as a clock pulse S5. The first output pulse S3 and clock pulse S5 from the ptSi pulse generation circuit 3 are generated by a D flip 70.
Given to whelk 6. This D7 lip-flop 6 has an input terminal, a clock pulse input terminal C, and an output terminal Q.

Next, the operation will be explained with reference to FIGS. 2 and 3. FIG. 2 is a waveform diagram when determining the first signal S1, and FIG. 1 (, ) shows the first trigger signal Sl' which is the positive differentiated output of the first signal S1. Figure 2 (b
) shows the first output pulse s3, and FIG. 2(c) shows the second output pulse s4.

FIG. 2(d) shows the clock pulse S5. As shown in FIG. 2, the period of each trigger signal Sl, S2 is 1/[
The output pulse width of the first output pulse S3 is longer than that of the second output pulse S2, and the output pulse width of the second output pulse S3 is longer than that of the second output pulse S2.
The output pulse width t2 of No. 4 is longer, and furthermore, this output pulse width L2 does not exceed the period 2/f2. Therefore, the clock pulse S5, which is output in synchronization with the falling edge (trailing edge) of the second output pulse S4, is always generated during the low level period of the first clock pulse S3. For this reason, the output terminal Q of D71j knob 70 knob 6 is connected to the output terminal Q shown in Fig. 2 (
As shown in e), a low level (L) output is generated. FIG. 3 is a waveform diagram when determining the second signal S2, and FIG. 3(a) shows the second tri-signal S2' as before. 3(b), (c), and (d) correspond to FIG. 2(b), (c), and (d-), respectively.

m31], the clock pulse S5 is always generated during the high level period of the first output pulse S3.

Therefore, the output terminal Q of the D7 lip 70 tube 6 receives a high level (H) output as shown in FIG. 3(e). In this way, according to this embodiment, when the first and second signals SL and S2 are input to the input terminal IN, it is determined from the output level of the D7 lip 70 knob 6 which signal was input manually. can do.

(Effects) As described above, according to the present invention, in the signal discrimination circuit that discriminates between the first signal having the frequency rl and the second signal having the frequency f2 (where 11<[2), each of the two signals is A circuit that generates a trigger signal corresponding to the cycle (1/[1, 1/12) of t2 big 1/f2<tl
<1/fl, 1/f1<L2<2/[2]. a second pulse generation circuit; a circuit that generates a clock pulse in synchronization with the trailing edge of the output pulse from the second pulse generation circuit; and a circuit that generates a clock pulse in synchronization with the trailing edge of the output pulse from the second pulse generation circuit; has a D flip 70 knob given, and said D
Since the two signals are discriminated depending on whether the output level of the flip 70 tube is high level or low level, even if there is a level difference between the signals to be discriminated, there is no need to make adjustments based on this level difference. Discrimination can be easily made.

[Brief explanation of drawings]

The drawings relate to an embodiment of the present invention, and the f:tS1 diagram is a circuit diagram of this circuit, FIG. 2 is a waveform diagram for explaining the operation corresponding to the first signal S1, and the third circle is the second signal S2. , 1.2. ,, 1st. The second bird is a signal generation circuit, 3°46
1. 1st. second pulse generation circuit, 500. Clock pulse generation circuit, 6. ,, D-Flip 70 Tubu applicant Sharp Co., Ltd. agent Patent attorney Oka 1) Kazuhide

Claims (1)

[Claims] (1) In a signal discrimination circuit that discriminates between a first signal having a frequency rl and an MS2 signal having a frequency 12 (however, fl < f2), each of the two signals has a period (1/1
1.1/f2), and the trigger signal is given from the signal generation circuit, so that the pulse output widths are respectively tl and t2 (however, if ti < t2, then 1/ [2<tl<1/f1.1./
The first . a second pulse generation circuit; a circuit that generates a clock pulse in synchronization with the trailing edge of the output pulse from the second pulse generation circuit; the output pulse from the first pulse generation circuit is used as an input pulse; 1. A signal discriminating circuit having a D flip 70 knob given to the circuit, and discriminating between the two signals depending on whether the output level of the D7 flip 70 knob is a high level or a low level.