JPS606555B2 - Resistor structure of hybrid integrated circuit - Google Patents
Resistor structure of hybrid integrated circuitInfo
- Publication number
- JPS606555B2 JPS606555B2 JP55054968A JP5496880A JPS606555B2 JP S606555 B2 JPS606555 B2 JP S606555B2 JP 55054968 A JP55054968 A JP 55054968A JP 5496880 A JP5496880 A JP 5496880A JP S606555 B2 JPS606555 B2 JP S606555B2
- Authority
- JP
- Japan
- Prior art keywords
- nickel plating
- layer
- integrated circuit
- hybrid integrated
- nickel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Description
【発明の詳細な説明】
本発明は混成集積回路の抵抗体構造に関しト特にニッケ
ルメッキに依って抵抗体を形成するものに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resistor structure for a hybrid integrated circuit, and more particularly to one in which the resistor is formed by nickel plating.
一般に混成集積回路は基板上に導電路を形成し、半導体
素子等を固着すると共にカーボン粒子の混入されたペー
ストを導電路間に印刷することに依って抵抗体を形成す
るものである。Generally, in a hybrid integrated circuit, conductive paths are formed on a substrate, semiconductor elements and the like are fixed thereto, and a resistor is formed by printing a paste mixed with carbon particles between the conductive paths.
また混成集積回路基板に熱伝導性の良い金属を用いて放
熱効率を高めた混成集積回路が実用化されている。第1
図は金属基板を用いた混成集積回路の断面図であり、基
板1はアルミニウムを用いており、アルミニウムの表面
を陽極酸化することに依って酸化アルミニウムの絶縁薄
層2が形成され、更に絶縁簿層2上に絶縁を兼ねる樹脂
層3で銅箔を接着し、所望のパターンに導電路4を形成
した構造であり、導電路4上には半導体素子(図示せず
)等が固着される。更に所定の導電路間には抵抗体が形
成されるが抵抗体をカーボン粒子を用いて形成した場合
には層抵抗RSが最低で100程度のものを作るのが技
術的に限界であり、実用的には1000程度のものが最
低で、数オーム以下の低抵抗を混成集積回路内に作るこ
とは困難であった。Further, hybrid integrated circuits have been put into practical use in which heat dissipation efficiency is increased by using a metal with good thermal conductivity for the hybrid integrated circuit board. 1st
The figure is a cross-sectional view of a hybrid integrated circuit using a metal substrate. The substrate 1 is made of aluminum, and an insulating thin layer 2 of aluminum oxide is formed by anodizing the surface of the aluminum. It has a structure in which a copper foil is bonded onto a layer 2 with a resin layer 3 which also serves as an insulator, and a conductive path 4 is formed in a desired pattern, and a semiconductor element (not shown) or the like is fixed onto the conductive path 4. Furthermore, a resistor is formed between predetermined conductive paths, but if the resistor is formed using carbon particles, the technical limit is to create a layer resistance RS of at least 100, which is not practical. Generally speaking, the lowest resistance is about 1000, and it has been difficult to create a low resistance of several ohms or less in a hybrid integrated circuit.
そこでニッケルメッキに依って低抵抗を形成する方法が
開発された。これは所定導電路間に比較的厚くニッケル
メッキを行なうものである。しかしニッケルメッキで低
抵抗体を形成する場合には層が厚くなるので問題は無い
のであるが、一般の抵抗あるいは高抵抗を形成する場合
には層が薄くなるので問題が生じた。Therefore, a method of forming low resistance using nickel plating was developed. This involves relatively thick nickel plating between predetermined conductive paths. However, when forming a low resistance element with nickel plating, there is no problem because the layer becomes thick, but when forming a general resistor or a high resistance element, a problem arises because the layer becomes thin.
それは第1図に示す如く、比較的薄いニッケルメッキ層
5を導電路4間に形成すると、ニッケルメッキ層5と導
電路4との境界部6に亀裂が生じニッケルメッキ層5が
断線する欠陥があった。実験的に調べたところニッケル
メッキ層5の厚さが1ム以上では断線はほとんどなく、
1ム以下では急激に断線が増加し実用化が不可能であっ
た。本発明は上述した点に鑑みて為されたものであり、
ニッケルメッキ層の断線を除去し、高抵抗化を可能とし
た混成集積回路を提供するものである。As shown in FIG. 1, when a relatively thin nickel plating layer 5 is formed between the conductive paths 4, a crack occurs at the boundary 6 between the nickel plating layer 5 and the conductive path 4, causing a defect in which the nickel plating layer 5 is disconnected. there were. Experimental research has shown that when the thickness of the nickel plating layer 5 is 1 mm or more, there is almost no disconnection.
If it is less than 1 μm, the number of disconnections increases rapidly, making it impossible to put it into practical use. The present invention has been made in view of the above points,
The present invention provides a hybrid integrated circuit that eliminates disconnections in the nickel plating layer and enables high resistance.
以下図面を参照して本発明を詳細に説明する。第2図A
,B,Cは本発明の実施例を示す工程別断面図であり、
7は基板であり、熱伝導性の良いアルミニウムから成る
。The present invention will be described in detail below with reference to the drawings. Figure 2A
, B, and C are process-by-step cross-sectional views showing examples of the present invention;
7 is a substrate, which is made of aluminum with good thermal conductivity.
第2図Aに於いて、先す基板7の表面を陽極酸化するこ
とに依って酸化アルミニウムの絶縁薄層8を形成し、絶
縁薄層8上一面に絶縁性の接着樹脂層9を設け、この接
着樹脂層9に依って銅箔を接着する。銅箔は塩化第2鉄
等のエッチング液に依って定められたパターンにエッチ
ングされ導電路10が形成さる。この導電路10は絶縁
薄層8及び接着樹脂層9に依って基板7と電気的に絶縁
される。次に抵抗体を形成する部分、即ち所定の導電路
10の一部とその導電路10間に露出している接着樹脂
層9を除く全ての導電路10及び接着樹脂層9上にレジ
スト11をスクリーン印刷等に依って塗布しマスクを形
成する。更にメッキに依って抵抗体を形成する部分に活
性剤を付着し、その部分にだけニッケルが付着する様活
性化する。この様に形成された基板7はメッキ処理が為
される。メッキ処理は硫化ニッケル及び次亜リン酸ソー
ダ等から成る無電解〆ッキ液に基板7を浸すことに依っ
て行なわれ、レジスト11の付着していない導電路貴0
及び接着樹脂層9上にニッケルが析出し、第1のニッケ
ルメッキ層12が得られる。第1のニッケルメッキ層1
2の厚さは無電解〆ッキ液の温度及び濃度を適当に設定
し「基板7をメッキ液に浸している時間を決定すること
に依って制御できる。次に第2図Bに於いて、第1のニ
ッケルメッキ層12上にレジスト13を塗布する。In FIG. 2A, the surface of the substrate 7 is first anodized to form an insulating thin layer 8 of aluminum oxide, and an insulating adhesive resin layer 9 is provided over the entire surface of the insulating thin layer 8. The copper foil is bonded using this adhesive resin layer 9. The copper foil is etched into a predetermined pattern using an etching solution such as ferric chloride to form a conductive path 10. This conductive path 10 is electrically insulated from the substrate 7 by the insulating thin layer 8 and the adhesive resin layer 9. Next, a resist 11 is applied on all the conductive paths 10 and the adhesive resin layer 9 except for the part where the resistor is to be formed, that is, a part of a predetermined conductive path 10 and the adhesive resin layer 9 exposed between the conductive paths 10. A mask is formed by coating by screen printing or the like. Further, by plating, an activator is applied to the portion where the resistor will be formed, and activated so that nickel adheres only to that portion. The substrate 7 formed in this manner is subjected to a plating process. The plating process is carried out by immersing the substrate 7 in an electroless coating solution made of nickel sulfide, sodium hypophosphite, etc.
Then, nickel is deposited on the adhesive resin layer 9, and the first nickel plating layer 12 is obtained. First nickel plating layer 1
The thickness of plate 2 can be controlled by appropriately setting the temperature and concentration of the electroless plating solution and determining the length of time that the substrate 7 is immersed in the plating solution. , a resist 13 is applied on the first nickel plating layer 12.
レジスト13は第1のニッケルメッキ層12と導電路1
0との境界部14に生じる段差部分の近傍及び第1のニ
ッケルメッキ層亀2と導電路10とが重畳する部分を除
く、第1のニッケルメッキ層12の中央部に塗布される
。レジスト13が塗布された基板7を前述した無電解〆
ッキ液に浸し、第2のニッケルメッキ層15を境界14
近傍に析出させ、第1のニッケルメッキ層12より厚く
少なくとも1仏以上に形成する。第2図Aに於いて形成
したレジスト11及び第2図Bに於いて形成したレジス
ト13はトリクレン等の溶剤に依って溶解除去される。A resist 13 is formed between the first nickel plating layer 12 and the conductive path 1.
It is applied to the central part of the first nickel plating layer 12, excluding the vicinity of the stepped part that occurs at the boundary part 14 with 0 and the part where the first nickel plating layer 2 and the conductive path 10 overlap. The substrate 7 coated with the resist 13 is immersed in the above-mentioned electroless glazing solution, and the second nickel plating layer 15 is formed on the boundary 14.
It is deposited nearby and is formed thicker than the first nickel plating layer 12 and at least one layer thicker. The resist 11 formed in FIG. 2A and the resist 13 formed in FIG. 2B are dissolved and removed by a solvent such as trichlene.
レジスト11,13の除去と共にレジスト11,13上
に広がったニッケルも除去され、更に表面をブラッシン
グすることに依ってバリが取れ、第2図Cの如〈所定の
導電路10及び接着樹脂層9上に第1のニッケルメッキ
層12と第2のニッケルメッキ層15が残ころ。この様
にして形成された抵抗体の構造が第2図Cに示されてい
る。Along with the removal of the resists 11 and 13, the nickel spread on the resists 11 and 13 is also removed, and the surfaces are further brushed to remove burrs, and as shown in FIG. The first nickel plating layer 12 and the second nickel plating layer 15 remain on the roller. The structure of the resistor formed in this manner is shown in FIG. 2C.
第1のニッケルメッキ層12は接着樹脂層9と強固に密
着され、更に導電路10がニッケルと密着性の良い銅か
ら成るために導電路10と重さなる部分の接触抵抗は全
く無いと言えるので抵抗体への影響が無視でき、バラッ
キを減少させることができる。また断線が発生しやすい
境界部14上には第2のニッケルメッキ層15が第1の
ニッケルメッキ層12と密着して厚く形成されているた
め断線は生じ得ない。従ってニッケルメッキに依る高低
抗と低抵抗とを同一混成集積回路内に同時に形成可能と
なる。抵抗体としての抵抗値は第1のニッケルメッキ層
i2に依って決定され、即ち第22のニッケルメッキ層
15の端部間に存在する第1のニッケルメッキ層12の
距離〜幅及び厚さに被って決定されるが、第1のニッケ
ルメッキ層12は1舷以下に形成され、層抵抗RSが5
00〜1000程度の比較的高抵抗を得ることができる
。The first nickel plating layer 12 is firmly adhered to the adhesive resin layer 9, and furthermore, since the conductive path 10 is made of copper which has good adhesion to nickel, it can be said that there is no contact resistance at the part that overlaps with the conductive path 10. Therefore, the influence on the resistor can be ignored and variations can be reduced. Furthermore, since the second nickel plating layer 15 is thickly formed in close contact with the first nickel plating layer 12 on the boundary portion 14 where disconnection is likely to occur, disconnection cannot occur. Therefore, high resistance and low resistance due to nickel plating can be simultaneously formed in the same hybrid integrated circuit. The resistance value as a resistor is determined by the first nickel plating layer i2, that is, the distance between the ends of the 22nd nickel plating layer 15 to the width and thickness of the first nickel plating layer 12. The first nickel plating layer 12 is formed on one side or less, and has a layer resistance RS of 5.
A relatively high resistance of about 00 to 1000 can be obtained.
更に第1のニッケルメッキ層12は従来のカーボン抵抗
体と同様にトリミングすることも可能であり、全ての素
子を固着した後回路を動作した状態で調整することもで
きる。また第1のニッケルメッキ属官2は接着樹脂層9
及び絶縁薄層8を介して基板7に密着されるため抵抗体
に大電流を流した時に大量の熱が発生してもも基板7に
熱が伝わり効率よく放熱されるのでt電力容量の大きい
回路構成に有利である。上述の如く第1のニッケルメッ
キ層と導電路との境界部上に第2のニッケルメッキ層を
形成することに依り「断線が完全に防止され」ニッケル
メッキに依る高抵抗が実現可能となり、同一混成集積回
路内にニッケルメッキに依る高抵抗と低抵抗とを同時に
形成することができるものであり「従釆のカーボン抵抗
を用いることなく効率的な混成集積回路の製造が可能と
なるものである。Furthermore, the first nickel plating layer 12 can be trimmed in the same way as a conventional carbon resistor, and adjustments can be made while the circuit is in operation after all the elements are fixed. In addition, the first nickel plated metal layer 2 has an adhesive resin layer 9.
Since it is closely attached to the substrate 7 via the thin insulating layer 8, even if a large amount of heat is generated when a large current is passed through the resistor, the heat is transferred to the substrate 7 and is efficiently dissipated, resulting in a large power capacity. This is advantageous for circuit configuration. As mentioned above, by forming the second nickel plating layer on the boundary between the first nickel plating layer and the conductive path, "disconnection is completely prevented" and high resistance due to nickel plating can be achieved, making it possible to achieve the same It is possible to simultaneously form high resistance and low resistance in a hybrid integrated circuit using nickel plating, and it is possible to efficiently manufacture a hybrid integrated circuit without using a secondary carbon resistor. .
図面の簡単な説頚
第1図は従来例を示す断面図、第2図A,B,Cは本発
明の実施例を示す工程断面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a conventional example, and FIGS. 2A, B, and C are process sectional views showing an embodiment of the present invention.
7・・・・・’基板、8・・・・・・絶縁薄層、9・…
・・接着樹脂層、10…・・・導電路、11・・…・レ
ジスト、12・・・…第1のニッケルメッキ層、13…
…レジスト、14…・・・境界部、15・・・・・・第
2のニッケルメッキ層。7...' Substrate, 8... Insulating thin layer, 9...
... Adhesive resin layer, 10... Conductive path, 11... Resist, 12... First nickel plating layer, 13...
...Resist, 14...Boundary portion, 15...Second nickel plating layer.
第1図 第2図Figure 1 Figure 2
Claims (1)
前記導電路間を露出してレジストを塗布し前記露出した
部分にメツキ処理を行なつて形成された第1のニツケル
メツキ層と、該第1のニツケルメツキ層と前記導電路と
が重畳した境界部近傍にメツキ処理して前記第1のニツ
ケルメツキ層よりも厚く形成された第2のニツケルメツ
キ層とから成る混成集積回路の抵抗体構造。1 conductive paths formed on a hybrid integrated circuit board, a first nickel plating layer formed by exposing any of the conductive paths, applying a resist, and plating the exposed portions; A resistor structure of a hybrid integrated circuit comprising: a second nickel-plated layer formed thicker than the first nickel-plated layer by plating near the boundary where the first nickel-plated layer and the conductive path overlap.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55054968A JPS606555B2 (en) | 1980-04-24 | 1980-04-24 | Resistor structure of hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55054968A JPS606555B2 (en) | 1980-04-24 | 1980-04-24 | Resistor structure of hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56150845A JPS56150845A (en) | 1981-11-21 |
JPS606555B2 true JPS606555B2 (en) | 1985-02-19 |
Family
ID=12985452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55054968A Expired JPS606555B2 (en) | 1980-04-24 | 1980-04-24 | Resistor structure of hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS606555B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62503075A (en) * | 1985-06-03 | 1987-12-10 | ブル−スサ−ド,ロバ−ト | Pyramid weight plate exercise equipment |
JPH0220569U (en) * | 1988-07-25 | 1990-02-09 | ||
JPH07204292A (en) * | 1994-01-14 | 1995-08-08 | Nippon Kinzoku Kogyosho:Kk | Dumbbell |
TWI737425B (en) * | 2020-07-23 | 2021-08-21 | 大陸商慶鼎精密電子(淮安)有限公司 | Embedded circuit board and manufacturing method thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62174968A (en) * | 1986-01-29 | 1987-07-31 | Hitachi Ltd | Semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS423717Y1 (en) * | 1965-08-05 | 1967-03-03 | ||
JPS4525826Y1 (en) * | 1967-11-29 | 1970-10-07 | ||
JPS4935941A (en) * | 1972-06-19 | 1974-04-03 | ||
JPS5423427A (en) * | 1977-07-25 | 1979-02-22 | Toshiba Corp | Beam index television picture receiver |
-
1980
- 1980-04-24 JP JP55054968A patent/JPS606555B2/en not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS423717Y1 (en) * | 1965-08-05 | 1967-03-03 | ||
JPS4525826Y1 (en) * | 1967-11-29 | 1970-10-07 | ||
JPS4935941A (en) * | 1972-06-19 | 1974-04-03 | ||
JPS5423427A (en) * | 1977-07-25 | 1979-02-22 | Toshiba Corp | Beam index television picture receiver |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62503075A (en) * | 1985-06-03 | 1987-12-10 | ブル−スサ−ド,ロバ−ト | Pyramid weight plate exercise equipment |
JPH0220569U (en) * | 1988-07-25 | 1990-02-09 | ||
JPH07204292A (en) * | 1994-01-14 | 1995-08-08 | Nippon Kinzoku Kogyosho:Kk | Dumbbell |
TWI737425B (en) * | 2020-07-23 | 2021-08-21 | 大陸商慶鼎精密電子(淮安)有限公司 | Embedded circuit board and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JPS56150845A (en) | 1981-11-21 |
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