JPS6065358A - キヤツシユ制御方式 - Google Patents

キヤツシユ制御方式

Info

Publication number
JPS6065358A
JPS6065358A JP58173792A JP17379283A JPS6065358A JP S6065358 A JPS6065358 A JP S6065358A JP 58173792 A JP58173792 A JP 58173792A JP 17379283 A JP17379283 A JP 17379283A JP S6065358 A JPS6065358 A JP S6065358A
Authority
JP
Japan
Prior art keywords
area
resident area
memory
address
resident
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58173792A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0514292B2 (enrdf_load_stackoverflow
Inventor
Hideo Tamura
秀夫 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58173792A priority Critical patent/JPS6065358A/ja
Publication of JPS6065358A publication Critical patent/JPS6065358A/ja
Publication of JPH0514292B2 publication Critical patent/JPH0514292B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58173792A 1983-09-20 1983-09-20 キヤツシユ制御方式 Granted JPS6065358A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58173792A JPS6065358A (ja) 1983-09-20 1983-09-20 キヤツシユ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58173792A JPS6065358A (ja) 1983-09-20 1983-09-20 キヤツシユ制御方式

Publications (2)

Publication Number Publication Date
JPS6065358A true JPS6065358A (ja) 1985-04-15
JPH0514292B2 JPH0514292B2 (enrdf_load_stackoverflow) 1993-02-24

Family

ID=15967236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58173792A Granted JPS6065358A (ja) 1983-09-20 1983-09-20 キヤツシユ制御方式

Country Status (1)

Country Link
JP (1) JPS6065358A (enrdf_load_stackoverflow)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559201A (en) * 1978-06-30 1980-01-23 Fujitsu Ltd Buffer memory control system
JPS5619571A (en) * 1979-07-23 1981-02-24 Nec Corp Buffer memory unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559201A (en) * 1978-06-30 1980-01-23 Fujitsu Ltd Buffer memory control system
JPS5619571A (en) * 1979-07-23 1981-02-24 Nec Corp Buffer memory unit

Also Published As

Publication number Publication date
JPH0514292B2 (enrdf_load_stackoverflow) 1993-02-24

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