JPS6065340A - Microprogram control system - Google Patents

Abstract

PURPOSE:To prevent the deterioration of yield and to shorten the schedule of development for LSI chips by providing an auxiliary memory in an LSI chip and replacing a defective bit of a program memory with the correction data in order to relieve a defect of a memory part. CONSTITUTION:In case the n-th bit microprogram memory data bn is faulty, an enable signal 82 is set at 1. At the same time, the encoding data of (n) are applied to the encoding data 81. Therefore only the n-bit signal bn of a decoder (a) is set at 1; while 0 is delivered to all other decoder output signals b0-bn-1. Then the n-th bit selector cn selects the auxiliary memory data 7 and delivers this data as the n-th bit control data 9n. At the same time, the 0-th-(n-1)th bit selectors c0-cn-1 all select microprogram memory data b0-bn-1. These data are delivered as the control data of (n-1) bits.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system within a microprogram of a system LSI incorporating a microprocessor or microphone program.

Conventional LSI chips with a built-in microprogram memory have no spare memory for correction, and the microprogram memory has become a stand-alone device. All bits of the memory data output based on the memory address information given each time are used as control data.

However, as the capacity of the microprogram memory 7ti increases and the proportion of the memory area occupied within the LSI chip increases, certain bit defects occur in the output data of the microprogram memory due to gate defects in the memory area. There was a drawback that the yield of chips decreased. Furthermore, when developing an LSI that includes a microprogram memory as a custom LSI that forms part of a data processing device, a one-bit defect or an acid bit defect in the memory data may necessitate re-design and remanufacturing the LSI. Another disadvantage was that the development of the entire data processing device itself was sometimes slow.

Does the present invention address the above-mentioned conventional drawbacks? This was done after looking at the microprogram memory in the LSI chip, so that the IIF memory that corresponds to the microprogram memory was placed in a parallel column (if? By replacing the data with the correction data output from the memory unit and relieving the defective memory section, it is possible to prevent a decrease in the yield of LSI chips that are caused by bit defects in the memory output data as U2:J, or to remedy defective designs of LSI chips. ii.
It is an object of the present invention to provide a microprogram control method for a system LSI with a built-in microprogram of a microprogram size that can reduce the size of the microprogram. and,
Specifically, the LSI chip includes a microprogram memory, a pre-0nt memory that provides data for correcting defective bits of the microprogram memory, and a defective bit correction circuit for data replacement, and an LSI chip outside the chip. A correction data calculation circuit for outputting correction information is provided, and a part of the address information, which is given at least in part to the microprogram memory and the pre-11'J memory, is outputted to the LSI chip, thereby detecting defects in the microprogram memory. Correction information for replacing bits with spare memory data is obtained from the above address information outside the chip,
It is an object of the present invention to provide a microprogram control method characterized by manually inputting the correction information into an LSI chip and replacing defective bit data in a microprogram memory with spare memory data.

Hereinafter, the micro block control method according to the present invention will be explained as follows.
2I and an embodiment shown in FIG. 2 will be described.

10 out of 1 are LSI chips, and within the LSI chips 10 [
The micro program memory 1 and the spare memory 2 are connected to the memory address 5, and the memory address 5 is further outputted to the outside of the LS11F tube 10 and connected to the correction data calculation circuit 4. . The microprogram memory data 6, spare memory data 7, and correction data 8 output from the correction data correction circuit 4 are manually inputted to a defective bit correction circuit 31fC arranged outside the LSI chip 10. Control data 9 is output from the defective bit correction circuit 3.

The defective bit correction circuit 3 includes selectors CO to Cn of nf4 that manually input the n+l bit microprogram data 60 to 6n, an enable signal 82 indicating the presence or absence of a defective bit in the correction data 8, and encoded data indicating the position of the defective bit. 81 manually, n-bit signal 1) 0~
and a decoder a that outputs bn. Note that normal data that should be present in the defective bits of the microprogram memory 1 is written in advance in the spare memory 2.

Memory address 5 generated within the LSI chip 10 is
The microprogram memory 1 and the spare memory 2 in the LSI chip 10 are manually inputted, and the microprogram memory data 6 and the spare memory data 7 are outputted, respectively. At this time, if there is a defective bit in the microprogram memory data 6, the spare memory data 7 is replaced with defective bit data.
It becomes data information to be replaced. The memory address 5 is output to the outside of the LSI chip 10 and input to the correction data calculation circuit 4. The correction data n output circuit 4 checks in advance the defective bit position corresponding to the address 1/s of the microprogram memory 1, and stores the defective bit in the preliminary memory data 7.
The correction data 8 to be replaced with is output. Within this correction data 8, an enable signal 82 indicating the presence or absence of a defective bit and encoded data 81 indicating the position of the defective bit.
is the n-th bit selector Cn from the decoder selector CO.
A select control signal is output for each of the signals.

The selector co-cn of the defective bit correction circuit 3 has 0
Bit-th microprogram memory data 60 to n
Bit-th microprogram memory data 5 r+
The preliminary memory data 7, in which i corresponds to the input power it and -4, respectively, is input in common from the 0th bit selector CO to the nth bit selector cnt.

Next, the effect will be explained.

First, if there are no defective bits, the enable signal 82
0", the 0-bit signal bO to the n-th bit signal 6n of the decoder a are all 0", and the microprogram memo IJ terminal 60 is given from the θ-bit first selector CO to the n-bit selector cn. ~6n is 73
The selected control data 90 to 90 are outputted.

Next, the nth bit microprogram memory data 6
If n is a defective bit, enable signal 82 is 1″
is given by Further, the encoded data 81 is provided with the encoded data of n.

Therefore, only the n-bit self-signal bn of 1 decoder a +11
++, and the other decoder output signal -Fjf+)0-bn
All 0'' is output for I. Then, the n-th bit selector cn selects the spare memory data 7, and outputs it as the n-th bit control data 9n. Selector CO~Cn-
1, all microprogram memory data 60 to 6
n-1 is selected and output as n-1 bit control data. That is, the microprogram memory data 6o
Only ffLn bits of ~6n are replaced with spare memory data 7, and are output as defect-free control data 90~9n.

Note that the illustrated example is microprogram memory data 60.
Although the circuit configuration is such that only one defective bit out of n+1 bits I.about.6n can be repaired, the present invention is not limited to this example, and a circuit capable of repairing a plurality of bits is also possible. Further, the correction data calculation circuit 4 is connected to the microprogram memory 1.
In order to be more flexible than the defective bit position fRK, RO
When M is used, the circuit configuration becomes l'iil simple.

As explained above, the microprogram control method according to the present invention includes a spare memory that provides correction data for replacing the defective bit when there is a defective bit in the microprogram memory in the LSI chip.
By generating correction data corresponding to the defective bit position outside the LSI chip and inputting only the correction data to the LSI chip, it is possible to eliminate microcontrollers that have occurred due to design errors in LSI chips that have defective bits in the microprogram memory. This has the effect of repairing an LSI chip having a bit defect in the program memory. Then, by relieving defects in the memory section, we can reduce the yield loss of LSI chips due to bit defects and
Many effects can be obtained, such as reducing the occurrence of SI redesign and shortening the LSI development schedule.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a defective pit correction circuit shown in FIG. 1. 1... Micro program memory 2... Spare memory 3... Defect pit correction circuit 4.
...Correction data correction circuit 5...Memory address 6...Micro program memory data 7...Spare memory data 8...Correction data 9...Control data 10...LSI chip a... Decoder output mrf person Hiki ■-1, Zhong Co., Ltd.

Claims (1)

[Claims] The LSI chip includes a microprogram memory, a spare memory that provides data for correcting defective bits of the microprogram memory, data fff, and a replacement defective bit correction circuit, and a circuit for outputting correction information outside the chip. A correction data calculation circuit is disposed, and address information, which is given at least in part to the microprogram memory and the spare memory, is output to the outside of the LSI chip;
The correction information for replacing defective bits in the microprogram memory with spare memory data is inputted from the above address information outside the step, and the j+HE information is input into the LSI chip, thereby saving the defective bit data in the microprogram memory. A microprogram control method characterized by replacement with memory data.