JPS60133600A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a chip occupying area as small as possible by using a part of an encoder part and a decoder part of Hamming code in common. CONSTITUTION:One Hamming code read out from a memory cell 4 is selectively inputted to a parity syndrome formation circuit parts 1-3 through a bus and the syndrome outputs are decoded by decoders 15-21 to correct the error of the read-out Hamming code. A part of the outputs from the decoders 15-21 is outputted to data bus through multiplexers 25-28 and writing buffers 32-35 and the residual of the outputs is outputted to a parity bus through the multiplexers 22-25 and writing buffers 29-31. The information on both the buses is rewritten in the cell 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device incorporating a Hamming error self-correction circuit.

In recent years, soft errors have been automatically detected inside memory chips. Semiconductor memory devices incorporating an error self-correction circuit that corrects AD and outputs it outside the chip are attracting attention. When incorporating an error self-correction circuit (hereinafter referred to as a circuit), it is required that the 1GOO section occupies a small proportion of the chip area and that the delay time due to the EOO section is short. What type of gCO to incorporate is also determined from the above-mentioned operating point. The Hamming code, which is widely used at the system level, detects a single bit error in any bit of the information bit group to be checked and the added check bit group.
Since it can be modified, it is considered to be a method suitable for incorporating into a memory device with a multi-bit configuration.

To perform error correction using a Hamming code, an encoder section generates a check bit group from a group of information bits and generates a mink code, and a decoder decodes the read mink code and generates a correction signal.

The department feels safe.

This decoder section can be divided into a syndrome generation section that generates the read out No. 1 mink code color syndrome, and a syndrome decoder section that decodes the syndrome and generates an error correction signal as a raw DV.

Traditionally, at the system level, the encoder for this No-Mink code was constructed as a separate and independent circuit. As mentioned above, to incorporate tr, oc into a memory chip, E
It is essential that the CU section occupy 74% of the chip area, and from this point of view, it is a major drawback to keep the conventional encoder and decoder independent.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide a semiconductor memory device having an error self-correction circuit using a mink code, which occupies a smaller chip area.

According to the present invention, in a semiconductor memory device having an error self-correction circuit using a No. Mink code, a plurality of specific pieces of information out of a plurality of pieces of information bit data and a plurality of pieces of check bit data read out from a memory cell array. a first circuit section that receives bit data as an input and outputs first test bit data corresponding to the input; and an output of the first circuit section and a plurality of test bits read from the memory cell array. a second circuit section which receives as input second 1tL scan bit data corresponding to the input of the first circuit section of the data and outputs the syndrome corresponding to the input; a third circuit section that receives the output and the second test bit data as input and outputs the third test bit data; and the output of the third circuit section and the output of the first circuit section as inputs. , a semiconductor memory device characterized in that it includes a multiplexer circuit that selectively outputs one input is obtained.

Hereinafter, the present invention will be described in detail with reference to the drawings. Figure 1 shows a typical embodiment of the present invention, in which the information bits are 4 bits (1), 6. DI, D2, Da),
FIG. 2 is a diagram showing an example of the configuration of the EOO section according to the present invention when the parity bits are 3 bits (Po, P+, P2). This part is a parity/syndrono/generating circuit block in which the encoder section of the Normink code, ie, the υ parity generation circuit, and the syndrome generation circuit of the decoder section of the Hamming code are shared. In the conventional example, the parity generation circuit section and the syndrome generation circuit section operate independently, with the parity generation circuit section being activated only when information is written to a memory cell, and the syndrome generation circuit section being activated when information is written from a memory cell. It is activated to 1 only during a read 1- operation, and the outputs of the parity generation circuit section and the syndrome generation circuit section are output to the parity bus and the data bus through separate routes. In the case of this embodiment, the parity and syndrome generation circuit section 1.2.3 is activated in both the read operation and the write operation, and in both cases, the parity (PO, Pi, P2 ) and syndrome (SO-81-82).・Syndrome (So, S) occurs during read operation.
parity information (POO, 82) corrected using
It is necessary to output the parity (Po, p, . . . PIO, P2O) generated from the information bit group during the write operation.
Since it is necessary to output P2), a multiplexer circuit (22, 23, 24) is used to selectively switch both signals.
)Is required.

The operation of the error self-correction circuit section using the /.mink code according to the present invention will be explained based on FIG. First, the read operation will be explained. One Hamming code (Po, P+, P2, Do, D, , D2.1) read from memory cell 4
3) is output to the path, selectively input to the parity and syndrome generation circuit section 1.2.3, and the parity output P1
0. pr, , P'2 and syndrome output So, 81
, S2 are output. Syndrome output 5osS1,S
2 is decoded by the decoders 15 to 21 and read out Hamming code (Pos Pi, P2, DO, D
,, D2.1) If there is &ff in 3), correct it, poc,
P, 0. p, c, 1) oc, D10%D20.
]) 3c.

1) oo, Dlo, I) 20.1j3C1 is D) ut
and the multiplexer circuit 25.26.2
7.28 and write buffer 32.33.34.35
is output to the data bus through On the other hand, PoC, P, O
, P2O, P2O are multiplexer circuits 22.23.2
It is output to the parity path through the 4,254i write buffer 29.30.31. The information on the data bus and parity path is rewritten into the memory 4, and the read operation is completed. 41: When writing, the write data Do, D1])2, and D3 are read from I)ir and output to the data bus through the multiplexer circuit 25.26.27.28 and the write buffer 32.33.3435. Ru. The data output to the data bus is selectively manually inputted into the parity and syndrome generation circuit sections 1.2 and 2, and the parity P
Parity, which outputs ′o,11/, , p/,
pi, , l)/, , P'2 is the multiplexer 22.
23.24 and the write buffer 29.30.31 to the parity path. Information on the data bus and parity path is written into the memory cell, and the write operation is completed.

As described above, the semiconductor memory device having the error self-correction circuit using the Hamming code according to the present invention can operate in the same way as the conventional one, and moreover, it can share part of the encoder section and decoder section of the Hamming code. Because of this, the scale of the additional circuitry can be smaller than that of conventional ones, making it extremely useful.

[Brief explanation of drawings]

FIG. 1 shows i! using the Hamming code according to the present invention. ! I
b is a diagram showing the configuration of an EOO section of an embodiment of a semiconductor memory device having a self-correction circuit, in which 1.2.3... Parity, syndrome generation circuit block 1 4... Memory cell , 5.6.7.8.9.10.11.12, 13.14・
...Exclusive OR gate, 15.16.17.1H, 19, 20, 21... Decoder (NO) also gate). 22.23.24.25.26.27.28-...
・Multiplexer circuit, 29, :30,; (1, 32, 33, 34, ko 35...
...indicates write buffer 1, Po, P,,P2,P2O,13/,,P'
2 is parity piti No. 6, Do, Dl, 1] 2.1
) 3, Information Pit No. 13, So, S. S2 is a syndrome signal, P 00. PIO,P
20 is i! ! Parity pit signal after 49 correction 1) 60
．． Dlo, D20. D3u indicates the information pit signal after error correction 1E.

Claims (1)

[Claims] In a semiconductor memory device having an error self-correction circuit using Hamming codes, reading from a memory cell array
A first test bin that takes as input a plurality of specific information bit data and a plurality of information bit data, and outputs the first inspection bin 1 data that corresponds to the input. a circuit section, and an output of the first circuit section and second test bit data corresponding to the input of the first circuit section among the plurality of test bit data read from the memory cell array, A second circuit section that outputs the syndrome corresponding to the input; the output of the second circuit section and the second test bit are manually operated, and the third test bit data is input to the third test bit data. A semiconductor memory 1 characterized in that it includes a multiplexer circuit which receives an output of a circuit section and an output of the first circuit section and selectively outputs one of the inputs.